Subject: [sv-ac] my votes
From: John Havlicek (john.havlicek@motorola.com)
Date: Fri Sep 12 2003 - 07:31:22 PDT
All:
I vote YES on all my suggestions.
Here are my votes on Surrendra's:
1) YES.
2) NO. Here is my rationale. Moving unary ## with respect to binary
## makes no difference. Moving unary ## all the way up makes a lot
of difference. Should
a |-> ##2 b[*3]
mean
a |-> ##2 (b[*3])
as it does now, or should it mean
a |-> (##2 b)[*3]
as it would if unary ## were moved up in precedence to just below ",".
Consider also
##1 b intersect c vs. a ##1 b intersect c
Under the current precedence, this is
##1 (b intersect c) vs. a ##1 (b intersect c)
whereas moving unary ## up would give
(##1 b) intersect c vs. a ##1 (b intersect c)
3) YES.
4) YES.
Best regards,
John H.
> We have noticed some parsing issues with 3.1 I would like to track
> these, perhaps as a single item in the enhancement list. These issues
> are corrections, or minor adjustments.
> Below is the list:
>
> 1) Change the associativity of throughout to right. Currently, it is
> defined as left in Table 17.1
>
> Left associativity does not work as it creates
>
> a throughout b throughout c ##! d; (1)
>
> (a throughout b) throughout c ##! d; (2)
>
> (2) is incorrect as the first term must be a boolean, while (a
> throughout b) is a sequence
>
> 2) unary ## should have the higher precedence than binary ##, perhaps
> just below "," in Table 17.1.
>
> This make it more intuitive, such as
>
> ##1 a ##1 b #1 c
>
> (##1 a) ## 1 b ##1 c, rather than
>
> ##1 ( a ##1 b #1 c)
>
> Also, it works like arithmetic +, where unary + has a higher precedence
> than binary +
>
> 3) Allow clocked sequences(including multi-clock) to be parenthesized
>
> This will allow examples as
>
> sequence name;
>
> (@clk seq);
>
> endsequence
>
> sequence name;
>
> (@clk s1 ## @clk s2);
>
> endsequence
>
> sequence name;
>
> (@clk s1) ## (@clk s2);
>
> endsequence
>
>
>
> property name;
>
> (@clk s1) |-> (@clk s2);
>
> endproperty
>
> 4) Should we force parenthesis around the expression with local variable
> assignments, such as
>
> a ##1 (b, l1 = 4, l2 = 5) ##1 c
>
> Currently, you can write the above as
>
> a ##1 b, l1 = 4, l2 = 5 ##1 c
>
>
>
> In other places in Verilog () is used whenever ", " is used for
> assignments. Also, it makes it clear that ", "is tied to the preceding
> boolean, rather than the sequence
>
> Surrendra
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