Re: [sv-ac] $display in assertions

Subject: Re: [sv-ac] $display in assertions
From: Surrendra Dudani (Surrendra.Dudani@synopsys.com)
Date: Fri Sep 12 2003 - 19:03:44 PDT

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HI Surrendra;


>Another possibility is to modify $info,$warning,$error,$fatal as system
> functions returning values as:

One problem though with this is that these are currently system tasks
and can be embedded in design or testbench verilog, or the program block
as a statement to report information.

If one changes them to a function, then you will have an unused return value
that has to be ignored, and will be reported as a potential problem by good
lint tools.

Maybe we could extend the sequence element to allow a (system)task after
the comma. E.g

  (a ##1 b |-> c && d, $error());


The only other problem I see is the inversion we are making, as John wrote:

>reducing it to

>   <bad sequence>
>   |->
>   $error(<whatever>)

Properties are written as asserted, or expected and we get the error message,
via 'else statement'. This above example makes the property require an inversion.

I would prefer to keep the positive logic. Otherwise it will be a source of forgetfulnesss - forgetting to invert the operation.

I made a inversion mistake when I wrote:

    not (a |-> b ##1 c)

And should have instead written
    (a |->  not b ##1 c)



      Adam