FW: [sv-ac] System-Verilog assertions Question From Dan Jacobi

Subject: FW: [sv-ac] System-Verilog assertions Question From Dan Jacobi
From: Vassilios.Gerousis@Infineon.Com
Date: Mon Jun 09 2003 - 23:29:14 PDT

From Dan Jacobi

-----Original Message-----
From: Jacobi, Dan [mailto:dan.jacobi@intel.com]
Sent: Tuesday, June 10, 2003 7:25 AM
To: Peter Flake; Gerousis Vassilios (CL DAT CS)
Cc: sv-ac@eda.org
Subject: RE: [sv-ac] System-Verilog assertions Question From Dan Jacobi

I believe this should be the case however the semantics of such statements
should be defined in the LRM, this way all the CAD tools will Have an
aligned behavior.

We also should define the semantics of such assertion statements: assert
(cond1) assert (cond2) else $display("message");

Thanks
Dan Jacobi
Intel Corp.

-----Original Message-----
From: Peter Flake [mailto:Peter.Flake@synopsys.com]
Sent: Monday, June 09, 2003 1:44 PM
To: Vassilios.Gerousis@Infineon.Com
Cc: sv-ac@eda.org; Jacobi, Dan
Subject: Re: [sv-ac] System-Verilog assertions Question From Dan Jacobi

Hi Dan, Vassilios,

I think that the else keyword should associate like

if (cond1) if (cond2) $display ("message 1"); else $display ("message 1");

Regards,

Peter.

At 15:02 08/06/2003 +0200, Vassilios.Gerousis@Infineon.Com wrote:
>Forward From Dan Jacobi
>
>========================
>Hello All,
>
>My Name is Dan Jacobi, And I am working with the SV-BC committee mainly
>on BNF issues,
>
>I was wandering if some body can point out in the new System-Verilog
>3.1
LRM
>where the semantics of the following statement is defined
>
>assert (cond1) if (cond2) $display ("message 1"); else $display
>("message 1");
>
>
>The main problem is define to where we should associate the 'else'
>keyword
>
>If we associate it to the if keyword then message 1 will be displayed
>when both cond1 and cond2 are evaluated to a non-zero value and message
>2 will
be
>displayed if cond1 is evaluated to a non-zero value and cond2 is
>evaluated to a zero (or x or z) value
>
>If we associate the else keyword to the assert keyword then message 1
>will be displayed when both cond1 and cond2 are evaluated to a non-zero
>value
and
>message 2 will be displayed if cond1 is evaluated to a zero (or x or z)
>value and cond2 is evaluated to any value
>
>Thanks
>Dan Jacobi
>Intel Corp.

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