Subject: Re: [sv-ac] System-Verilog assertions Question From Dan Jacobi
From: Peter Flake (Peter.Flake@synopsys.com)
Date: Mon Jun 09 2003 - 03:43:35 PDT
Hi Dan, Vassilios,
I think that the else keyword should associate like
if (cond1) if (cond2) $display ("message 1"); else $display ("message 1");
Regards,
Peter.
At 15:02 08/06/2003 +0200, Vassilios.Gerousis@Infineon.Com wrote:
>Forward From Dan Jacobi
>
>========================
>Hello All,
>
>My Name is Dan Jacobi, And I am working with the SV-BC committee mainly on
>BNF issues,
>
>I was wandering if some body can point out in the new System-Verilog 3.1 LRM
>where the semantics of the following statement is defined
>
>assert (cond1) if (cond2) $display ("message 1"); else $display ("message
>1");
>
>
>The main problem is define to where we should associate the 'else' keyword
>
>If we associate it to the if keyword then message 1 will be displayed when
>both cond1 and cond2 are evaluated to a non-zero value and message 2 will be
>displayed if cond1 is evaluated to a non-zero value and cond2 is evaluated
>to a zero (or x or z) value
>
>If we associate the else keyword to the assert keyword then message 1 will
>be displayed when both cond1 and cond2 are evaluated to a non-zero value and
>message 2 will be displayed if cond1 is evaluated to a zero (or x or z)
>value and cond2 is evaluated to any value
>
>Thanks
>Dan Jacobi
>Intel Corp.
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