Subject: Re: [sv-ac] alternative proposal to "syn1": remove binary delay
From: Adam Krolnik (krolnik@lsil.com)
Date: Tue Feb 11 2003 - 08:40:48 PST
Hi Cindy;
Here are some sequence examples that I would like to see if the
current proposal works with them.
Specifications:
1. A and 2 cycles later B
2. A and 1 or 2 cycles later B
3. A followed by seqC (seqC is C now or in 10 cycles.)
4. A implies B (same cycle)
5. A implies B (in next cycle)
5. A implies B in the next 1 to 10 cycles.
Alternative to syn1:
1. (A; [2] b) ok
2. (A; [1:2] b) ok
3. sequence seqC = ([1:10] c);
(A; seq) missing A&C as legal.
4. (A => B); ok
5. (A => [1] B) incorrect.
6. (A => [1:10] B) missing cycle 10 since A => B is same cycle.
These can be fixed by rewriting them as:
3 ???
5. (A => [2] B) though seems to say 2 cycles later
6. (A => [2:10] B) <same reasoning>
LRM 0.79:
1. (A; [2] b) ok
2. (A; [1:2] b) ok
3. sequence seqC = ([0:10] c);
(A; seq) ok.
4. (A => b); ok
5. (A => [1] b); ok
6. (A => ([1:10] b) ok.
Is this accurate? How would one rewrite #3 for alternative to syn1 ? Which is better?
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
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