Subject: Re: [Fwd: Re: [sv-ac] check: How will we do this?]
From: Adam Krolnik (krolnik@lsil.com)
Date: Tue Feb 11 2003 - 08:15:50 PST
Good morning Prakash;
After considerations for and against the check statement both by you and
myself, here is my proposal and justification.
I propose that the check statement be removed for the following reasons:
1. The functionality is very limited.
a) You are only allowed a boolean expression argument
b) Its use is limited to clocked RTL (design) procedural blocks
[It has uses in the testbench, but still is limiting.]
2. I would prefer to have a unified "assert" statement with full support
for properties and sequences to be used in all contexts.
3. It is easier to extend or add functionality than to remove it.
We can work on this functionality for the next SystemVerilog release.
In place of the check statement, one can always use
if (! boolean_expr) $error();
Thanks
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
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