Subject: RE: [sv-ac] Question about reference to data defined in sequence.
From: Jay Lawrence (lawrence@cadence.com)
Date: Wed Feb 05 2003 - 17:05:09 PST
Yes, as you all know, I don't attend sv-ac, but have been watching
templates with interest. They seem an interesting general purpose
extension that is specifically being introduced for assertions but have
broader implications. For instance, there is no reason they contain
properties at all. They just provide a macro capability on steroids, so
users no longer have to put \\ on the end of multiple lines of a macro.
If the entire thing is defined as text substitution by a pre-processor
(and you handle Erich's comments on redeclaration of names used as
formal arguments), then they need no semantic explanation at all. It is
all just a text substitution and the semantics is left up to
SystemVerilog.
Jay
===================================
Jay Lawrence
Architect - Functional Verification
Cadence Design Systems, Inc.
(978) 262-6294
lawrence@cadence.com
===================================
> -----Original Message-----
> From: Adam Krolnik [mailto:krolnik@lsil.com]
> Sent: Wednesday, February 05, 2003 7:49 PM
> To: Jay Lawrence
> Cc: bassam@novas.com; john.havlicek@motorola.com;
> Surrendra.Dudani@synopsys.com; sv-ac@eda.org
> Subject: Re: [sv-ac] Question about reference to data defined
> in sequence.
>
>
>
>
> Hi Jay;
>
> >The precedent set by Verilog-1364 here (in section 19.3.1
> on `define)
>
>
> I see, so we should be saying in the LRM,
>
> An instantiation of a template shall be replaced using the
> text substitution facilities
> of SystemVerilog.
>
> Or something similar, to clearly show that templates are part
> of the preprocessor facility.
>
>
> More questions, see you tomorrow.
>
> Adam Krolnik
> Verification Mgr.
> LSI Logic Corp.
> Plano TX. 75074
>
>
>
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