Re: [sv-ac] Question about reference to data defined in sequence.

Subject: Re: [sv-ac] Question about reference to data defined in sequence.
From: Adam Krolnik (krolnik@lsil.com)
Date: Wed Feb 05 2003 - 16:48:56 PST

Next message: Jay Lawrence: "RE: [sv-ac] Question about reference to data defined in sequence."
Previous message: Erich Marschner: "RE: [sv-ac] Question about reference to data defined in sequence."
In reply to: Jay Lawrence: "RE: [sv-ac] Question about reference to data defined in sequence."
Next in thread: Erich Marschner: "RE: [sv-ac] Question about reference to data defined in sequence."
Reply: Adam Krolnik: "Re: [sv-ac] Question about reference to data defined in sequence."
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

Hi Jay;

>The precedent set by Verilog-1364 here (in section 19.3.1 on `define)

I see, so we should be saying in the LRM,

An instantiation of a template shall be replaced using the text substitution facilities
of SystemVerilog.

Or something similar, to clearly show that templates are part of the preprocessor facility.