Re: [sv-ac] specific proposal

Subject: Re: [sv-ac] specific proposal
From: Adam Krolnik (krolnik@lsil.com)
Date: Wed Feb 05 2003 - 11:44:03 PST

Hi John;

Questions, questions - no answers.

This proposal creates another element, a formula, similar to sequences and boolean
(declarations.)

So we can declare

formula a = (something);
sequence b = (soemthing);
bool c = (something);

Is there value in the ability to declare all three?
Would it be sufficient to just factor sequence implication up to the clocked_sequence
level as in:

   clocked_sequence :== [event_control] sequence_expr
     | [event control] sequence_expr => sequence_expr

For formulas, you allow:

sequence => sequence

Which we talked about. You also allow:

   sequence => sequence => sequence
   ((int somevar = something) formula)

Is it valuable to have these two additional abilities (from one who has not worked
with formulas)?

    Thanks.

    Adam Krolnik
    Verification Mgr.
    LSI Logic Corp.
    Plano TX. 75074

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