Subject: RE: [sv-ac] Additional though on Assertion templates
From: Erich Marschner (erichm@cadence.com)
Date: Wed Dec 04 2002 - 14:00:07 PST
Adam,
I see your point.
One argument that might be made for templates is the fact that System Verilog Assertions includes procedural assertions, for which component instantiation (of modules) would not work (since component instantiation cannot take place within a procedural block). Then again, one could also argue that, if a template contains multiple definitions, the semantics of invoking it within procedural code could be quite complex - or else the restrictions on what can be invoked within procedural code would be perhaps equally complex.
Perhaps modules could be used as you suggest, instead of templates, to encapsulate a set of definitions and directives that can be invoked in either of two ways: by instantiating the module, or by invoking definitions within the module. In the former case, the module would include ports and assertions about those ports; instantiation would connect the appropriate signals to those ports and thus to the assertion instances. In the latter case, the module would include parameterized property declarations which could be invoked directly, either as declarative assertions or as procedural assertions.
For example, something like this:
module Template (a, b, c);
input a, b, c;
assert (if a) (b[2]; c[3]);
assert (if c) ([5]; a);
endmodule;
vs.
module Library;
property P1(a,b,c) = (if a) (b[2]; c[3]);
property P2(c,a) = (if c) ([5]; a);
endmodule;
Module Template can be instantiated as a set of declarative assertions, much like OVL today. In contrast, the properties in module Library could be invoked elsewhere, individually, e.g.
assert Library.P1 (x,y,z);
anywhere the property itself would be legal - e.g., either in a declarative or a procedural context.
I'm not sure whether the latter would require any changes in Verilog scoping rules, but I'm sure those could be accomodated if need be.
Does this make sense?
Regards,
Erich
-------------------------------------------
Erich Marschner, Cadence Design Systems
Senior Architect, Advanced Verification
Phone: +1 410 750 6995 Email: erichm@cadence.com
Vmail: +1 410 872 4369 Email: erichm@comcast.net
| -----Original Message-----
| From: Adam Krolnik [mailto:krolnik@lsil.com]
| Sent: Wednesday, December 04, 2002 11:50 AM
| To: sv-ac@eda.org
| Subject: [sv-ac] Additional though on Assertion templates
|
|
|
|
| Good morning;
|
| I was thinking more about the assertion templates.
|
| While the BNF at the end of the document is cut off, section
| 11.11 shows the
| template containing properties, directives, sequences and
| bool declarations.
|
| Everyone has agreed that additional logic (sattelites, fsms,
| etc) will be required
| for some kinds of properties. Thus for this class of
| properties one will have
| to use a module to encapsulate (for reuse) the assertions.
|
| Does this mean templates should allow for logic to be created?
| Does this mean modules should be favored over templates?
|
|
| Thanks.
|
|
| Adam Krolnik
| Verification Mgr.
| LSI Logic Corp.
| Plano TX. 75074
|
|
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