[sv-ac] Additional though on Assertion templates

Subject: [sv-ac] Additional though on Assertion templates
From: Adam Krolnik (krolnik@lsil.com)
Date: Wed Dec 04 2002 - 08:50:11 PST

Good morning;

I was thinking more about the assertion templates.

While the BNF at the end of the document is cut off, section 11.11 shows the
template containing properties, directives, sequences and bool declarations.

Everyone has agreed that additional logic (sattelites, fsms, etc) will be required
for some kinds of properties. Thus for this class of properties one will have
to use a module to encapsulate (for reuse) the assertions.

Does this mean templates should allow for logic to be created?
Does this mean modules should be favored over templates?

    Thanks.

    Adam Krolnik
    Verification Mgr.
    LSI Logic Corp.
    Plano TX. 75074

This archive was generated by hypermail 2b28 : Wed Dec 04 2002 - 08:51:38 PST