Re: [sv-ac] Final SV-AC Requirements Results


Subject: Re: [sv-ac] Final SV-AC Requirements Results
From: Adam Krolnik (krolnik@lsil.com)
Date: Tue Oct 08 2002 - 09:49:50 PDT


Good morning;

I was reading the ballot results and saw a few strange voting patterns.
Anyone care to comment... Any other strange results IYO?

for/against votes
8/5 "R74" "Define recommended method to separate design code

  I'm surprised there wasn't much support for this - very cheap and
  easy to support (by users/tools.)

8/4 "R1d" "Assertions must be embedded directly in-line with
6/7 "R6" "Pass/fail statement for declarative assertions"
  Seems to conflict with
12/1 "R5a" "Declarative assertions as well as procedural"
14/1 "R5b" "Declarative assertions inside of
modules/interfaces"

  While everyone was for declarative/procedural assertions and being
  part of a module or interface, there was less support for actually
  supporting the desire with an implementation. Is this freedom from
  specific requirements to allow DWG to define as they desire?

8/4 "R29a" "Optional user-specified unique name for
assertions"
7/5 "R29b" "Mandatory user-specified unique name for
assertions"
  Seems to conflict with
15/0 "R20" "Ability to define/declare reusable sequences
(and
                         refer to them by name)" "SM3, TF3"
13/1 "R80a" "Language shall define the status of specified
named
                         assertion(s)" "SD56"

  While support for naming sequences and status of named assertions was
  desirable support for naming of assertions was not very desirable.
  Somewhat strange too.

  Thanks all.

    Adam Krolnik
    Verification Mgr.
    LSI Logic Corp.
    Plano TX. 75074



This archive was generated by hypermail 2b28 : Tue Oct 08 2002 - 09:51:56 PDT