Subject: RE: [sv-ac] Re: Action items for Rajeev Ranjan
From: Ambar Sarkar (ambar.sarkar@paradigm-works.com)
Date: Thu Aug 22 2002 - 07:34:34 PDT
Shalom,
I have to disagree..as long as there are no other drivers, I expect the
sensitivity list will ensure the order...I expect the following
sequence:
1. a1, b1 change at the same instant(in the active list)
2. a2, b get assigned (non-blocking assigns complete) a does not since
a2 has not changed yet.
3. a gets assigned (non-blocking)
Maybe I 'm missing something?
Anyways, regardless of the order, the basic question remains...can we
specify a property about glitches?
Regards,
-Ambar
--
Ambar Sarkar Email:
ambar.sarkar@paradigm-works.com
Principal Consulting Engineer Phone: 978-824-1363
Paradigm Works Cell: 508-561-1868
-----Original Message-----
From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of
Shalom Bresticker
Sent: Thursday, August 22, 2002 10:20 AM
To: Ambar Sarkar
Cc: Rajeev Ranjan; sv-ac@eda.org
Subject: Re: [sv-ac] Re: Action items for Rajeev Ranjan
I believe it is not necessarily true that
"a will get its final value one delta time later than b".
In fact, a may even get its final value before b.
Shalom
Ambar Sarkar wrote:
> For example, can we create a property saying "no glitch on
sampled_signal"
> as shown below?
>
> assign sampled_signal = a ^ b;
>
> always (a2)
> a <= a2;
> always (a1)
> a2 <= a1;
>
> always (b1)
> b <= b1;
>
> Notice that even if a1 and b1 are sampled at the same design clock, a
will
> get its final value one delta time later than b.
> A glitch will be seen when a1 and b1 both start as 1, and then both
change
> to 0.
--Shalom Bresticker Shalom.Bresticker@motorola.com
Design & Reuse Methodology Tel: +972 9 9522268
Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890
POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478
"The devil is in the details."
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