Subject: Re: [sv-ac] Re: Action items for Rajeev Ranjan
From: Shalom Bresticker (Shalom.Bresticker@motorola.com)
Date: Thu Aug 22 2002 - 07:19:51 PDT
I believe it is not necessarily true that
"a will get its final value one delta time later than b".
In fact, a may even get its final value before b.
Shalom
Ambar Sarkar wrote:
> > For example, can we create a property saying "no glitch on sampled_signal"
> > as shown below?
> >
> > assign sampled_signal = a ^ b;
> >
> > always (a2)
> > a <= a2;
> > always (a1)
> > a2 <= a1;
> >
> > always (b1)
> > b <= b1;
> >
> > Notice that even if a1 and b1 are sampled at the same design clock, a will
> > get its final value one delta time later than b.
> > A glitch will be seen when a1 and b1 both start as 1, and then both change
> > to 0.
-- Shalom Bresticker Shalom.Bresticker@motorola.com Design & Reuse Methodology Tel: +972 9 9522268 Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478"The devil is in the details."
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