RE: WG Ballot - Accept closure of http://www.eda-stds.org/mantis/view.php?id=3386

I'm in favor of closing this issue as irrelevant for 'e'.
Regards,
Gery O.

-----Original Message-----
From: owner-ieee1647@eda.org [mailto:owner-ieee1647@eda.org] On Behalf Of
darren.galpin@infineon.com
Sent: Thursday, June 26, 2014 12:16 AM
To: ieee1647@eda.org
Subject: WG Ballot - Accept closure of
http://www.eda-stds.org/mantis/view.php?id=3386

Hi,

This is an e-mail ballot on http://www.eda-stds.org/mantis/view.php?id=3386.
The summary is as follows:-


Summary:                    Consider adding wildcard equality operators
Description:
Consider adding wildcard equiality operators ==?
and !=? like in SystemVerilog, where x and z values act as wildcard.


Comment from IEEE-SA ballot, to consider for future version.
======================================================================

----------------------------------------------------------------------
 (0016233) Yuri Tsoglin (developer) - 2014-06-25 08:42
 http://www.eda-stds.org/mantis/view.php?id=3386#c16233
----------------------------------------------------------------------
I propose to close this issue.
We already have operators === and !== (section 4.10.3 in the 2011 version of
LRM), which provide this ability between HDL objects and e expressions.

Applying the same to e expressions in general would be irrelevant. Unlike
SystemVerilog (which is based on Verilog in the first place), e is not based
on HDL language, and as such it doesn't have at all the notion of x and z
values for its native expressions.

In addition, we already have MVL capabilities for simple ports (sections
9.9 and 9.10 in the 2011 version), which also handle x and z values in a
way.




So, the ballot question is as follows:-

Do you accept closing this issue as rejected on the basis that it applies to
HDL languages only?



The ballot will be open for a week. Feel free to add any points of
discussion to the issue via the reflector.

Cheers,

Darren

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