2010-01-27
Attendees:

000000000000000100001011110000000000000 Qamar Alam
111111111111111111101011111110111111011 Himyanshu Anand
011111111001111110111010001111111111111 Kenneth Bakalar
111110101011011011101100001110001110101 Prabal Bhattacharya
000000000000001100001010010000100100000 Sri Chandra
011110111111111111011010111110111110001 Eduard Cerny
111011100001011010111011111011111110101 Scott Cranston
000000000000000100000000000000010000001 Dave Cronauer
000000000000110000000001111110011110111 Dejan Nickovic
110111011110010000000000000000000000000 Mike Demler
000000000000000000000000000000000000000 Surrendra Dudani
111000000011111111111100110111111111111 John Havlicek
111000110010000000000000000000000000000 Kevin Jones (RGG Leader)
000000011111111110111011111111111111111 Jim Lear
000000000000111011100000000000000000001 Top Lertpanyavit
111111011011111111111111101111111111111 Scott Little
000000000000010000000000000000000000000 Erik Seligman
101000000000000000000000000000000000000 David Sharrit
000000010000000000000000000000000000000 Murtaza
000000010000000000010110011000000100100 Martin O'Leary

Summary:
-Himyanshu Anand's role has changed at Freescale and he may not have the time to continue in his role leading the group. He suggested that Scott Little take over. There were no objections.
-The P1800 SystemVerilog committee is having an open meeting to discuss issues regarding the next PAR. This committee is going to prepare a presentation for that meeting. Ken Bakalar will put together a draft which can be discussed over the next two weeks. The deadline for presentation submission is 2010.02.12.
-The technical work relating to the requirements needs to move forward. Ken Bakalar suggested that there are three primary areas of focus:
1. determining how to embed the assertions within the current languages
2. the real-time extensions to the language
3. Synchronization between analog and digital engines
-Volunteers to work on the focus areas are as follows:
1. Ken Bakalar
2. Dejan Nickovic, John Havlicek, Himyanshu Anand, Scott Little
3. Jim Lear, Prabal Bhattacharya, Scott Cranston

Action Items:
-Scott Little will updated the requirements section of the web.
-Ken Bakalar will create a first draft presentation for the P1800 SystemVerilog open meeting to be held on 2010.02.26. The presentation is due to Karen Pieper by 2010.02.12.
-John Havlicek will send out information regarding how to get involved in the P1800 committee.

Details:

HA: My role has changed in Freescale. I would like to suggest that Scott Little take over my role. Are there objections?

KB: No objection
EC: No objection
TL: No objection
PB: No objection
SC: No objection

HA: I will still attend, but with my new role I am afraid I can't dedicate the necessary time.

SL: The P1800 SystemVerilog committee is holding an open meeting following DVCON to discuss the next PAR. I believe that we should do a presentation at this meeting.

JL: I presume that we would just talk about requirements.

SL: That seems reasonable.

JH: The meeting is to drive next PAR. We should try to talk about things to facilitate what we need to do the A-SVA work.

JL: What is the structure of the P1800 committee?

JH: There is one working group and 4 regular committees under that basic committee (BC), extensions committee (EC), assertions committee (AC), and C-interface (CC). There was briefly under the last PAR a special committee, but my understanding is that it was dissovled. There is also the champions group that review proposals out of all the groups. They are sort of a filter for the working group.

JL: Who is chair of BC?

JH: Matt Maidment of Intel chairs BC, Mehdi Mohtashemi of Synopsys chairs EC, Dmitry Korchemny of Intel chairs AC, Swapnajit Mittra of SGI chairs CC.

JL: Could you send out a bit of information about how to get involved in P1800 committee?

JH: Yes.

HA: Presentation must be ready by 02-12 for prior review.

JH: The challenge to us is to get together whatever we want to present by the 12th.

HA: What level of detail is required?

JH: It is up to the person presenting. It should be at a level that is relevant for making decisions about what to include in the PAR. I have seen some presentations that have a lot more detail than others.

HA: Each working group elects a person to present at the meeting?

JH: I don't know. I would expect that the presenters are representing specific entities like companies or committees.

SL: Does someone want to create this presentation?

KB: If it is just the requirements that doesn't seem to hard. I guess I am volunteering. I would encourage that it be presented and authored from the perspective of the users.

JH: I think we ought to include examples.

KB: I think that putting syntax in is dangerous. It would be nice if SV-VAMS committee would be presenting as well and could give a bit of perspective where we fit.

SL: I don't think anyone from FSL will be present.

KB: That is too bad. Are other member companies going to be present?

SL: I believe that there will be virtual meeting facilities.

JH: This is intended to be a face to face, but there will be virtual meeting facilities present.

KB: The presentation is done remotely by whoever and whoever is in the room is in the room.

JH: You are also free as entities of whoever you are to give your own views of this work and how P1800 should be working with us. Those would be the opinions of your own group and not this group.

SL: I would like to take a look at the requirements and assign them out to different entities to produce a technical document. This isn't going to be a final proposal, but it should contain many of the technical details and directions.

KB: I am not sure that each requirment deserves its own proposal. Why don't we look at them as two larger tasks. One task is the definition of extended SVA. The other task is the embedding task.

SL: That is largely true. Some of Jim's tasks don't quite fit into those categories though.

KB: There is a third task which is the synchronization. You would like to be able to control the analog timestep and take samples without synchronizing the analog solver. There are several issues with coordinating the analog engine and the digital engine.

JL: My requirements revolve around providing an adequate data set. Some of them also apply to discrete time simulations outside the realm of analog simulation.

KB: I believe that an FFT is something that you need built-in.

JL: I don't know as as I agree.

SL: Okay, well it sounds like Ken has volunteered for embedding, Freescale for assertions, and Jim for synchronization.

JH: I think that if we are splitting it up into 3 buckets then we need larger groups.

DN: I would be willing to participate in the assertion language stuff with Freescale.

PB: Cadence is willing to participate with the synchronization. Scott Cranston do you have a preference?

SC: I would prefer to work on the language requirements.

-- ScottLittle - 2010-01-27