Accellera Verilog Analog Mixed-Signal Group

The Verilog-AMS Technical Subcommittee has been created under the auspices of Accellera with the charter to develop, update and promote analog and mixed signal extensions to the Verilog (IEEE-1364) language. This activity has resulted in the Accellera approval of the Verilog-AMS LRM, version 2.3.1, in June 2009. This version supersedes the OVI Verilog-A LRM (from June 1996) and previous versions of the Verilog-AMS LRM.

The next goal of the committee will be alignment of Verilog-AMS with the SystemVerilog work of IEEE 1800, or inclusion of AMS capabilities in a new "SystemVerilog-AMS" standard. In addition, a subcommittee is working on clearing up ambiguities in the mixed-signal areas of the LRM.

Anyone may join the committee or its e-mail reflector; details can be found here.

Verilog-AMS benefits users by allowing them to describe and simulate analog and mixed signal designs using a top-level design methodology as well as the traditional bottom up approaches. The Verilog-AMS standard supports analog and mixed signal designs at three levels: transistor/gate, transistor/gate-rtl/behavioral, and mixed transistor/gate-rtl/behavioral circuit levels. Moreover, Verilog-AMS provides powerful structural and behavioral modeling capabilities for systems in which the effects of, and interactions among, different disciplines like electrical, mechanical and thermal are important.

The goal of this work group is to make sure that analog, mixed signal and system designers can find relevant information on the Verilog-AMS, from activities to technical data on how to better use these extensions.

-- DavidMiller - 2011-01-25

Topic revision: r2 - 2011-01-26 - 22:27:11 - DavidMiller
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