System Verilog Basic Committee (SV-BC)


The SV-BC is the technical subcommittee of the IEEE P1800 Working Group that is tasked with maintaining and extending the design and foundational features of the System Verilog language. Currently the SV-BC is combined with the SV-EC and working on both design and testbench issues.

Email Reflector

The SV-BC uses the email reflector SV-BC@LISTSERVENOSPAM.IEEENOSPAM.ORG for most of its regular communication. Subscription instructions can be found here.

Email communication prior to January 2016 is archived for reference.

Issue Database

All IEEE 1800 Issues are tracked in the Accellera Mantis Hub.

Meeting Logistics

  • The committee is wrapping up work under the 2016 1800 PAR for editorial updates, errata and clarifications.
  • Meetings are scheduled bi-weekly on Tuesdays of even workweeks from 8am-10am PT.
  • Call Logistics are included with meeting notices emailed to the reflector.

  • Meeting Minutes
March 15, 2016

March 29, 2016

April 12, 2016

April 26, 2016

May 10, 2016

June 21, 2016

July 19, 2016

September 13, 2016

October 11, 2016

October 25, 2016

-- Matt Maidment - 2016-03-29


Topic revision: r7 - 2016-11-01 - 17:59:56 - MattMaidment
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