Recent Changes in P1076 Web retrieved at 17:55 (GMT)

P1076 Working Group Public Documents These documents are for anyone with interest in the IEEE P1076 Working Group P1076 wg individual 2015.doc: P1076 Working...
P1076 March 3, 2016 Meeting Minutes Attendees: Rob Gaddi, Ernst Christen, Patrick Lehmann, Peter Flake Agenda: Meeting Discussion What`s Next see PrivateDocuments...
Subprograms ## Single syntax for functions and procedures to do without declaration and definition regions. E.g.: package subs is end package subs; package body subs...
Bundles Proposal Details Who Updates: LievenLemiengre Date Proposed: 2016 04 12 Date Last Updated: 2016 04 12 Priority: high Complexity:...
Record Reflection Use Case To Std Logic Vector So one of the things I frequently have to do is transform record types to and from std logic vector. Vendor provided...
RecordIntrospection Use Case `ToJson` This use case demonstrates the usage of the proposed introspection capabilityto convert a complex data structure (nested records...
Minimal RTL Record Based Interface Use Case Assumptions This use case is intended to propose a minimal implementation of an enhanced interface support for RTL...
VHDL 200X FT 17 Composite Interface Mode Enhancement Detail: Give VHDL the ability to specify the IO mode of an element of a record. Useful for testbenches and...
IR2089: Directional Records Description of Problem For many standard interfaces, for instance a bus, there are input and signals. Both can be combined into a record...
IR2067: Logical link interface abstraction Description of Problem It is quite common that one logical connection between two component instances consists of several...
Interfaces: Packages as an Interface Construct Current VHDL: The Basics Signals declared in a package are accessible to any model that accesses the package. For each...
Interface Construct and Port Mode Configurations Implementation details Interface Construct: interface declaration :: interface identifier of composite subtype...
Add a `Bus` port mode for bidirectional port signals Proposal: Add a new mode in addition to (in, out, buffer, inout, linkage), tentatively called `bus`.`bus` is...
Candidate: Resolved Records Use records as an inout and require that each element of the record have a resolution function. This methodology is currently under usage...
7. Historical Discussion 7.1. Phone Discussion with Cliff Notes from Cliff on SV Interfaces Interfaces are good but often overhyped. Testbench ip developer can...
6. Interface Implementation 6.1. Base line Implementation Interfaces are a methodology. As such to implement them, it is permissible to leverage existing constructs...
5. Things Reflected upon for VHDL 2008 revision, and then we ran out of time. These are not solutons for going forward 5.1. Composites: Resolving Values vs. Specifying...
4. Current Capabilities At a bare minimum an interface is a composite with a method to group the subprograms together. To some degree, this can be done using a record...
3.2. RTL Design, Subprogram Usage, and Hardware Creation 3.2.3. Simple Interfaces A simple interface packages subprograms with bundles. A block (such as B1) calls...
3.2. RTL Design 3.2.1. Simple Bundles Connectivity of RTL functions consists of one or more signal objects. A bundle is a simplified form of an interface that allows...
3.1. Transaction Based Testbench 3.1.1. Basic Transactions A transaction is an operation on a device interface. As such it could be a cpu read or a cpu write. A transaction...
Placeholder page for this proposal For now you can take a look at the attachments I quickly hacked the modifications into our compiler both files already pass syntax...
Status Quo and Moving Forward with Bundles Ernst Christen, Mentor Graphics The Status Quo Since its first version in 1987, VHDL has supported design entities with...
Heterogeneous Interfaces with Emphasis on Reusing Existing VHDL Concepts Proposal Details Who Updates: ErnstChristen Date Proposed: 2015 11 05 Date...
Candidate 1: Bundles specified as a type definition Think of a bundle as being an enhanced version of a record. A bundle uses the concept of conjugated modes, while...
Heterogeneous Interfaces with Emphasis on Compactness Proposal information Who Updates: ErnstChristen, ... Date Proposed: Date Last Updated:...
Defining Interface Bundles Based on Record Types or Array Types An Analysis Ernst Christen, September 30, 2015 Updated October 8, 2015: Clarifications and corrections...
Interface and Bundle Requirements Accepted Requirements (draft) The interface construct was originally prompted by the requirement for better support in order...
Accellera VHDL TC Extensions SC Interfaces Jim Lewis, SynthWorks jim #64;synthworksNOSPAM.com Version 0.1 Draft, 12 Jan 2006 Abstract This paper covers the requirements...
2. Introduction An interface is an abstract representation of the connectivity and communication between two or more objects. This abstract representation may be implemented...
Interface Discussions Pages for the bullet points and questions relating to various aspects of the proposed new Interface construct. Heterogeneous Interface Requirements...
Object Introspection in VHDL Proposal Details Who Updates: Jing Pang Date Proposed: 2015 7 15 Date Last Updated: 2015 7 15 Priority: Complexity...
Simple record based interface One reason that the interface proposal was initially put forward: engineers want to put their structural level signal interconnects...
Overview of SystemVerilog Interfaces Introduction The concept of an interface has been part of SystemVerilog since the Accellera 3.0 version of the language. According...
Bundles in VHDL Introduction This page discusses issues around defining the concept of a bundle in VHDL. We use the term bundle here instead of interface to distinguish...
New Interface Port/Parameter Mode Requirements From an RTL perspective... A new `interface` construct with a primary aim to capture customized mode structures...
Heterogeneous Interfaces Ernst Christen, Mentor Graphics 1. Introduction As part of the work on P1076 201x, several proposals have been made that aim at providing...
Interface Bundle Requirements Interfaces were originally conceived as using the standard record type to group various signal types together. A VHDL AMS...
Additional Interface Related Proposals Interfaces: Attributes for Interfaces provides new attributes to shortcut support for new interface modport construct...
Additional Rules for Bit String Literals Proposal Details Who Updates: DanielKho Date Proposed: Date Last Updated: Priority: Complexity:...
Overloaded Assignments Proposal Details Who Updates: AndyJones Date Proposed: 2013 05 03 Date Last Updated: Priority: Complexity: Focus...
Issue Screening and Analysis Committee (ISAC) Language Clarification Proposals These proposals are intended to clarify current language features that have clarification...
The idea proposed here is to use a standard preprocessor like cpp or m4. For that to work, a standard set of pre defined variables is still needed that reflect the...
This approach is to standardize on a set of pragmas(simple tool directive) that today are a proprietary pragma definition or structured comment in the VHDL language...
Hi David, I can try and motivate the include concept first, and then open the can and look into that. You aren t the first to ask why we need it, but so far I felt...
P1076 Voting Information Call for Vote closes 10 Aug 5 pm Pacific To vote, you must, have a twiki account (Participating) and add yourself...
P1076 13 July 2011 Voting Item 1: Operating Procedures for P1076 Working Group http://www.eda.org/vasg/docs/p1076 wg pp.pdf Approve Negative Abstain...
P1076 10 Aug 2011 Voting Vote closed at 5pm US PDT, on Wednesday 10 August, 2011. At the July 28, 2011 meeting it was decided to propose that the working group policies...

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