Language Change Specification for Interface Construct and Port Mode Configurations Proposal Primary LCS: This LCS details the minimum support required for a mode...
SPI Interface Use Case Introduction Working through the SPI bus using LCS 2016 45 Port Views plus LCS 2016 70 Space Ship Use case has One QSPI bus master...
Master, 4 slaves, Separate Decode and Mux block, Separate/Individual Slave Busses Introduction Working through Rob`s example using LCS 2016 45a Port Views plus LCS...
Standard VHDL Preprocessor The proposed solution is a standard set of preprocessing directives. It should properly fit with the VHDL standard tool directive that was...
Master, 4 slaves, Shared Decode and Mux block Introduction Working through Rob`s example using LCS 2016 45 Port Views plus LCS 2016 70 SpaceShip Use case has...
Master, 4 slaves, Shared Decode and Mux block Introduction Working through Rob`s example using LCS 2016 45 Port Views plus LCS 2016 70 SpaceShip Use case has...
Brent Master Multiplexer with Multiple slaves Introduction Working through the Brent`s Master with Multiplexer Example LCS 2016 45 Port Views plus LCS 2016 70 SpaceShip...
Language Change Specification for Scalar Attributes and Function Reference Proposal (spinoff from FunctionKnowsVectorSize) LCS Number: LCS 2016 072a Version...
Reflection Proposal Details Current Situation Generically converting types from one kind to another currently isn`t possible in VHDL. This causes a lot of code duplication...
The bugzilla report 293 states that it is unclear whether the alternative label possible in an if or case generate statement forms part of the path name. The proposed...
Language Change Specification for Deferred Shared Variables Proposal Primary LCS: This is the main LCS describing the changes to support extended deferred object...
Language Change Specification for Record Introspection Indexing Primary LCS: This LCS details changes to a record declaration and selected name definition in order...
Language Change Specification for Record Introspection Indexing Secondary LCS: This LCS details changes for an attribute to provide introspection of record types...
P1076 October 27, 2016 Meeting Minutes Attendees: Patrick Lehmann, Rob Gaddi, Peter Flake, Jim Lewis, Brent Hayhoe, Agenda: Meeting Discussion Interfaces...
Complex RTL Record Based CPU Interface Use Case Introduction The concept of this use case is to arbitrarily introduce a fairly complex block and interface structure...
AHB Lite Modified Interface Adapted to use the new bundle structure as discussed in the WG meeting on 22nd September 2016. Example Code Support Package...
P1076 August 25, 2016 Meeting Minutes Attendees: Rob Gaddi, Kevin Jennings, Lieven Lemiengre, Patrick Lehmann Agenda: Discussion and Approve Meeting...
Revised SPI Example What is SPI? SPI refers to any number of variations on a 4 wire serial bus. The master asserts the chip select (usually active low) and then performs...
Semi Complex RTL Record Based SPI Interface Use Case Introduction The SPI bus having existed since slightly before the wheel, it presents a familiar use case to introduce...
package util is type logger is protected procedure log(msg : string; sev : severity level); end protected; end package; library ieee; use ieee.std logic...
Interface Semantics Discussion Interface construction within VHDL is largely supported by composite types, which include array types and record types. These allow...