VHDL202xCollectedRequirements < P1076

P1076 Web>VHDL202xCollectedRequirements (2020-04-28, PeterLadow) (raw view)EditAttach
---+ Proposal Summary + Link to Proposals

Status Values:
   * RAW - Initial development, may change frequencly, comments welcome
   * RFC - Draft, needs comments
   * REVIEW - Requesting more formal review in working group meeting
   * STABLE - Done
   * LCS - LCS Editing, Volting, Approval, or Rejection in process

<table border="1" cellpadding="0" cellspacing="1"> <tbody> <tr> <td>
---+++ *Item*
 </td> <td>
---+++ *Who*
 </td> <td>
---+++ *Status*
 </td> <td>
---+++ *LCS Link*
 </td> <td>
---+++ *Description*
</td> </tr> <tr> <td>File IO / Textio Updates</td> <td> </td> <td>RAW</td> <td><a href="LCS2016_006a" target="_blank">LCS2016_006a</a></td> <td> </td> </tr> <tr> <td>File IO / Directory IO</td> <td> </td> <td> </td> <td><a href="LCS2016_006c" target="_blank">LCS2016_006c</a></td> <td> </td> </tr> <tr> <td>Sequential Declaration Regions (corresponding short form)</td> <td> </td> <td> </td> <td>

<a href="LCS2016_007" target="_blank">LCS2016_007</a>
<a href="LCS2016_007a" target="_blank">LCS2016_007a</a> </td> <td> </td> </tr> <tr> <td>Date/TIme Functions</td> <td> </td> <td> </td> <td><a href="LCS2016_011" target="_blank">LCS2016_011</a></td> <td> </td> </tr> <tr> <td>Attributes for Enumerated Types</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>New Attributes</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>'designated_type</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Indexing Constrains from Initial Values for Signals and Variables</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>LongIntegers</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Selected names for types (implementation of external names for types)</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Garbage Collection</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Protected Types with Generic Clause</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Allow for conditional expressions in a declaration (baseline)</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Record Introspection Type Reflection</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Interface - defines new mode view construct for composite interfac objects</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Interface - `CONVERSE for a mode view</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Protected Type: Shared Variables on Entity Interface</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Map Generics on Subprogram Call</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Array Type Generics</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Allow odering on any scalar array - related to Array Type Generics</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Bidirectional Connections</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Function Knows Return Vector Size</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Closes related record types</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>All Interface Lists Can Be Ordered</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Conditional Return Statement</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Extended Ranges</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Updating IEEE Standard References</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Repair example in Section 5.6.3</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Precedence of Unary Operators</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Repair Example in Section 23.21</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>DREAD, DWRITE, Integer D, H, O B Read and Write</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Allow access to system environment variables</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Deferred Shared Variables</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Deferred Shared Variables</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Extenstion to LCS 099 - intended to make things more locally static</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Generate Statement Alternate Path Names - beware of pathname for external names vs RV'path_name</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Generate Statement Alternate Path Names - Dissentiing Opinion</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>'access attribute</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Long Integers - 512 bit</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Long Integers - 64 bit integer and subtypes</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Long Integers - 64 bit integer and 32 bit integer</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Anonymous types for external names (implementation of external names for types)</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Interface - defines new null mode for composite interface element actual/formal isolation</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Additional Operators to Integers</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Wait Level - Signal Expressions in Signal Parameter Map</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Bidirectional Connections</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Extra comma at the end of lists</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Fix 2008 Context Clause</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>The sensitivity list for process(all) should not include signals in all reachable subprograms</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Protected Types with Public Signals</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Package as an Interface Construct</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Implicit Parameter and Port connectinos</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Bidirectional Connections</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Closely related record types</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Record Introspection</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Record Introspection and Indexing</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Process-All and Implicit Signals</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Package Name Case Sensitivity</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Integers of arbitrary length</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Long Integers 64 bit type</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Modular Integer Types</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Additional Operators for Integers - Logic</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Implicit Conversions for Like Types</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Extended Integers</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Physical Type Range</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Enhanced Integers</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Modify Report Statement to return calling path of subprograms</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>DPI Proposal</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Hierarchical Libraries</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>External names for types</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Configuration Spec for Direct Instances</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Attributes for PSL</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Protected Types with Wait and Private Signals</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>API for Assert</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Slicing Multidimensional Arrays</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>External Non-Shared Variable Name</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>New Predefined Attributes: actual and formal</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Abstract Packages</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Wait with Level Check</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Unions and/or Variant Records</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Expressions in Bit String Literals - Dynamic Sizing</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Relaxed OTHERS rules in aggregates</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Deferred Shared Variables</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Overload Assignment Operator</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Extended String Literals</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Extended Ranges</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Extended user-defined attributes</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Access to logic representation of VHDL objects</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>numeric_std, fixed, and float bugs adn consistency updates</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Real Matric Math Package</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Flag metavalues detected by ??</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Read differences of bit_vector and std_logic_vector</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Updates to standard packages - split into LRM and Packages</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Signatures for Association List Aspects</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Assigning 2008 Entities to Attributes Classes</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Repair LRM Example 14.2</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Repair LRM Example 7.3.2.1</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Repair Text on Context Clauses</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Repair LRM Section 16.8.2.4.3 Missing Paragraph Text</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Repair example in LRM section 5.6.3</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Bit String Literals Corner Cases</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Repair Generate Statements</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Force and Out Port</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>String Representation for extended identifiers</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Alternate Label in Path Nume Bug 293</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Repair Example in Sectdion 23.21</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Typographical Issues in IEEE Std 1076-2008</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Process-All should not be sensitive to signals in packages</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>VHPI Impact</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>VHPI for PSL</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>define parameters for env.stop</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Standard instances of float</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Vector literal introspection</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Object orientation</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Wait with repeat count</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Cross Language Instances</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>std_ulogic, resolved, and '-'</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Create natural_vector</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Architecture generic</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Multiple top-level designs</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Preponed processes (clocks)</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Update std_logic_arith</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Dynamic process, instances, fork/join</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Shorthand subprogram declarations</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Sequential signal declarations</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Truth tables</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Asynchronous channels</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Clocked shorthand</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Dynamic rewiriing</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Composing path to external names</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Attribute shorthand</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Support synthesis of reals</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Named package bodies</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Unique condition - Orlf</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Synthesizable reports and assertions</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Multicycle path specification</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>2 and 4 state values</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Specify timign constraints</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Synthesizable 'event attribute</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Object inspection</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Use of unicode</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Move definition of TEXT, INPUT, OUTPUT</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Stop Binary/Octal/Hex Read At trailing underscore</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td colspan="5">
---++++ VHDL AMS 1076.1 Proposals
</td> </tr> <tr> <td>Table Driven Modeling</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr> <td>Vector/Matrix Package</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> </tbody> </table> -- <span data-mce-mark="1">%USERSIG{PeterLadow - 2020-04-28}%</span>

---++ Comments

<br /><span data-mce-mark="1">%COMMENT%</span>
Topic revision: r1 - 2020-04-28 - 22:26:31 - PeterLadow
P1076