Truth Tables

Proposal Editing Information

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  • Date Last Updated:
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Requirement Summary

Related Issues: ISAC IR-2060

-------------BEGINNING OF IR----------------

VHDL Issue Number:        2060

Language_Version          VHDL-2002
Classification            Language Modeling Enhancement or Deficiency
Summary                   Include truth table for multi-input/multi-output logic.
Relevant_LRM_Sections     
Related_Issues            
Key_Words_and_Phrases     truth table
Authors_Name              J D Russell
Authors_Phone_Number      39-295-4004
Authors_Fax_Number        
Authors_Email_Address     jdrussel@rockwellcollins.com
Authors_Affiliation       
Authors_Address1          
Authors_Address2          
Authors_Address3          

Current Status:           Forwarded

Superseded By:

------------------------
Date Submitted:           26 January 2005
Date Analyzed:
Author of Analysis:
Revision Number:          1
Date Last Revised:        05 February 2005

Description of Problem
----------------------

Complex logic functions with numerous inputs (with don't cares), and
numerous outputs (with don't cares), are difficult to express in VHDL.
They are easily expressed compactly with a simple truth table.

Proposed Resolution
-------------------

A syntax similar to that of Altera's AHDL would suffice.  Or something
like this:
    
    table (in1,in2,in3 :in; out1,out2 :out) begin
            0 , - , 1 ,      1  , -   ;
            1 , 1,  0 ,      0  , 0   ;
    end table;
    
    Outputs default to don't care for all inputs not explicitly defined.
    
    
    

VASG-ISAC Analysis & Rationale
------------------------------

This should be forwarded to the Modeling and Productivity Group

VASG-ISAC Recommendation for IEEE Std 1076-2002
-----------------------------------------------
TBD

VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
TBD


-------------END OF IR----------------

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Topic revision: r2 - 2016-06-09 - 18:41:42 - RobGaddi
 
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