Typographical Issues in IEEE Std 1076-2008

This is a collection of typographical issues in the LRM that are not captured by their own pages.

Subclause 5.3.2.1 General

A constrained array definition similarly defines both an array type and a subtype of this type:

  • The array type is an implicitly declared anonymous type; this type is defined by an (implicit) unbounded array definition, in which the element subtype indication either denotes the base type of the subtype denoted by the element subtype indication of the constrained array definition, if that subtype is a composite type, or otherwise is the element subtype indication of the constrained array definition, and in which the type mark of each index subtype definition denotes the subtype defined by the corresponding discrete range.
Rationale: The FrameMaker source for P1076-2008 contains a note by Peter Ashenden: The word “and” was deleted by the IEEE copy editor in the published version of 1076-2008. The word is required for the intended meaning. —PA

ErnstChristen -- 2016-11-10

Subclause 6.5.2 Interface object declarations

The sentence

If no mode is explicitly given in an interface declaration other than an interface file declaration, mode in is assumed.

should read

If no mode is explicitly given in an interface object declaration other than an interface file declaration, mode in is assumed.

Rationale: This section, while subordinate to 6.5 Interface declarations, includes text specific to interface object declarations. If the intent of the sentence were to apply to all interface declarations, it would be in the wrong place. Moreover, modes only apply to interface object declarations, not to interface declarations in general.

ErnstChristen -- 2016-05-04

Note 8: The second occurrence of vhpi_put_value should also be rendered in fixed-width font.

ErnstChristen -- 2016-11-08

Subclause 6.5.7.3 Port map aspects

The text

The purpose of a port aspect is as follows:

should read

The purpose of a port map aspect is as follows:

Rationale: There is no concept called "port aspect" in 1076-2008, and the section is about port map aspects.

ErnstChristen -- 2016-05-04

Subclause 9.2.3 Relational operators

In the text

Relational operators include tests for equality, inequality, and ordering of operands. The operands of each relational operator shall be of the same type. The result type of each ordinary relational operator (, /, <, <=, >, and >=) is the predefined type BOOLEAN. The result type of each matching relational operator (?=, ?/=, ?<, ?<=, ?>, and ?>=) is the same as the type of the operands (for scalar operands) or the the element type of the operands (for array operands).</p?

the duplicate word the should be deleted.

ErnstChristen -- 2017-01-25

Subclause 10.3 Assertion statement

A line feed (LF) format effector occurring as an element of the message string is interpreted by the implementation as signifying the end of a line. The implementation shall transform the LF into the implementation-defined representation of the end of a line.

Rationale: The FrameMaker source for P1076-2008 contains a note by Peter Ashenden: The index marker for “line feed” was deleted during copy editing for 1076-2008 publication. It is retained here. —PA

ErnstChristen -- 2016-11-10

Subclause 12.3 Visibility

A declaration is visible only within a certain part of its scope; this part starts at the end of the declaration except in the declaration of a design unit other than a PSL verification unit, a package declaration, or a protected type declaration, in which case it starts immediately after the reserved word is occurring after the identifier of the design unit, a package declaration, or protected type declaration. This rule applies to both explicit and implicit declarations.

Rationale: The FrameMaker source for P1076-2008 contains a note by Peter Ashenden: Delete the spurious word “a” missed by copy editor for 1076-2008 publication. —PA

ErnstChristen -- 2016-11-10

Subclause 14.2 Elaboration of a design hierarchy

In the lettered list, item a), the word Elaboratiaon should be replaced by Elaboration.

ErnstChristen -- 2017-01-27

Subclause 16.7 Standard multivalue logic package

In the lettered list, item c), the text says that "The STD_LOGIC_TEXTIO package is empty …". However, the package downloadable from the IEEE web site contains 12 alias declarations, i.e. it's not empty.

ErnstChristen -- 2017-03-21

Subclause 24.1.1 General

This is the clause about standard tool directives.

In the example at the end of this section, the original protect directive and the equivalent sequence of protect directives should use the same font size.

ErnstChristen -- 2016-05-11

Subclause 24.1.3.1 Encoding methods

In the second row of the table body, there should be a space between uuencode and -m: IETF RFC 2045 [B22] {also IEEE Std 1003.1-2004 [B11] (uuencode -m)}

Rationale: The FrameMaker source for P1076-2008 contains a note by Peter Ashenden: In 1076-2008, the space before the -m command-line option was deleted by the copyeditor. The space is required and is retained here. —PA

ErnstChristen -- 2016-11-10

Subclause G.2.3 Handling strengths

Once in forcing strength, the model can simply respond to 'X's, '0's, '1's, and 'U's as the need may arise. This strength stripping is done by using one of the following functions:

Rationale: The FrameMaker source for P1076-2008 contains a note by Peter Ashenden: The opening quotes are omitted from 'X', '0', and '1' in 1076-2008. This was not picked up by the IEEE copyeditor. —PA

ErnstChristen -- 2016-11-10

Subclause G.2.9.1 Use of the don’t care state in synthesis models

For synthesis, a VHDL program is a specification of the functionality of a design. VHDL can also be used to model (in order to simulate) real circuits. The former deals with logical function of the circuit, while the latter is concerned with function of a circuit from an electrical point of view. The nine-state logic type usage for synthesis is based on the assumption that the VHDL models will be logical function specifications and, therefore, attempts to restrict the usage of the logic type to logical function. The motivation for allowing the user to reference the values 'U' and 'X' (which do not specify the behavior of the circuit to be built, i.e., one can not build a circuit which “drives an 'X'”) is to allow such simulation artifacts to remain in models for synthesis for the sake of convenience. By having synthesis remove these references, the user is assuming only the kind of usage (of 'U' and 'X') that catches error states that should never occur in hardware.

Rationale: The FrameMaker source for P1076-2008 contains a note by Peter Ashenden: This was incorrectly changed to “attempt” by the IEEE copyeditor. The original word [attempts] is retained here. —PA

ErnstChristen -- 2016-11-10

Comments

Topic revision: r9 - 2017-04-02 - 16:23:11 - PatrickLehmann
 
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