Language Change Specification for Protected Type: Shared Variables On Entity Interface

LCS Number: LCS-2016-047
Version: 5
Date: 19-Feb-2017
Status: Voting
Author: Jim Lewis
Email: Main.JimLewis
Source Doc: Protected Type: Shared Variables On Entity Interface
History Doc: LCS2016_047_history
Summary: Protected Type: Shared Variables On Entity Interface

Style Notes

Changes are shown in red font. Deletions are crossed out. Editing notes in green font.

Details of Language Change

6.4.2.3 Signal declarations

47.1: [Edit: Note 1 on page 69 at the end of 6.4.2.3] NOTE 1-Ports of any mode are also signals. The term signal is used in this standard to refer to objects declared either by signal declarations or by signal port declarations (or to subelements, slices, or aliases of such objects). It also refers to the implicit signal GUARD (see 11.2) and to implicit signals defined by the predefined attributes 'DELAYED, 'STABLE, 'QUIET, and 'TRANSACTION. The term port is used to refer to objects declared by port declarations only.

Section 6.5.2 Interface object declarations

47.2: [Note: paragraph 1 needs the edit from LCS_2016_034 if is not accepted]

47.3: [Edit: Note 3 on page 75 at the end of 6.5.2] NOTE 3-Signal ports Ports of mode linkage are used in the Boundary Scan Description Language (see IEEE Std 1149.1TM-2001 [B15]).

47.4: [Edit: Note 5 on page 75 at the end of 6.5.2] NOTE 5-The driving value of a signal port that has no source is the default value of the port (see 14.7.3.2).

47.5: [Edit: Note 7 on page 75 at the end of 6.5.2] [if Note 7 is not already deleted, delete it and make note 8, note 7] NOTE 7-Although ports of mode out have identical semantics to ports of mode buffer, there is an important design documentation distinction between them. It is intended that a port of mode out should be read only for passive activities, that is, for functionality used for verification purposes within monitors or property or assertion checkers. If the value of an output port is read to implement the algorithmic behavior of a description, then the port should be of mode buffer. Due to the potential complexity of monitors and checkers, it is not feasible to express these usage restrictions as semantic rules within the language without compromising the ability to write complex monitors and checkers.

47.6: [Edit: Note 8 on page 75 at the end of 6.5.2] NOTE 8-A signal port of mode in may be updated by a force assignment, a release assignment, or a call to vhpi_put_value. A formal parameter of mode in shall not be updated by a call to vhpi_put_value (see 22.5.1).

Section 6.5.6.1 General (Interface lists)

47.7: [Edit: page 78, 3rd paragraph, BNF counts as a paragraph]

A generic interface list consists entirely of interface constant declarations, interface type declarations, interface subprogram declarations, and interface package declarations. A port interface list consists entirely of interface signal declarations and interface variable declarations. A parameter interface list may contain interface constant declarations, interface signal declarations, interface variable declarations, interface file declarations, or any combination thereof.

6.5.6.3 Port clauses

47.8: [Edit: page 79, 3rd paragraph of 6.5.6.3]

The ports of a block are defined by a port interface list. Each interface element in the port interface list declares a formal port. If a formal port does not explicitly specify the object class, signal is assumed. A formal variable port shall be of a protected type and shall have a port of mode inout.

47.9: [Edit: page 79-80, Last paragraph 79, First 80]

To communicate with other blocks, the ports of a block can be associated with signals or shared variables in the environment in which the block is used. Moreover, the signal ports of a block may be associated with an expression in order to provide these ports with constant driving values or with values derived from signals and other ports; such ports shall be of mode in. A port is itself a signal (see 6.4.2.3); thus, a formal port of a block A formal signal port is itself a signal (see 6.4.2.3), and thus, may be associated as an actual with a formal signal port of an inner block. A formal variable port is a reference to a shared variable, and may be associated as an actual with a formal variable port of an inner block. The port, signal, shared variable, or expression associated with a given formal port is called the actual corresponding to the formal port (see 6.5.7). The actual, if a port, or signal, or shared variable, shall be denoted by a static name (see 8.1).

47.10: [Edit: page 80, First whole paragraph]

[Note: the following text comes from LCS_2006_122, which adds signal expressions to ports]

If a formal signal port of mode in is associated with an expression that is not globally static (see 9.4.1) and the formal is of an unconstrained or partially constrained composite type requiring determination of index ranges from the actual according to the rules of 5.3.2.2, then the expression shall be one of the following:

47.11: [Edit: page 80, 3rd paragraph]

If the actual part of a given association element for a formal signal port of a block is the reserved word inertial followed by an expression, or is an expression that is not globally static, then the given association element is equivalent to association of the port with an anonymous signal implicitly declared in the declarative region that immediately encloses the block. The signal has the same subtype as the formal signal port and is the target of an implicit concurrent signal assignment statement of the form

47.12: [Edit: page 80, 2nd to last paragraph]

After a given description is completely elaborated (see Clause 14), if a formal signal port is associated with an actual that is itself a port, then the following restrictions apply depending upon the mode (see 6.5.2), if any, of the formal signal port:
a) For a formal signal port of mode in, the associated actual shall be a port of mode in, out, inout, or buffer. This restriction applies both to an actual that is associated as a name in the actual part of an association element and to an actual that is associated as part of an expression in the actual part of an association element.
b) For a formal signal port of mode out, the associated actual shall be a port of mode out, inout, or buffer.
c) For a formal signal port of mode inout, the associated actual shall be a port of mode out, inout, or buffer.
d) For a formal signal port of mode buffer, the associated actual shall be a port of mode out, inout, or buffer.
e) For a formal signal port of mode linkage, the associated actual may be a port of any mode.

47.13: [Add: page 80, before last paragraph]

[Note: putting this here because the adjacent paragraphs talk about actual ports. Someday maybe, we will move these to 6.5.7.3]

The actual associated with a formal variable port shall either be a shared variable or a formal variable port of another design entity, and shall be a protected type. The association of an actual with a formal variable port results in the actual passing a reference to the formal.

47.14: [Edit: page 80, last paragraph]

[WRT the strike out of the reference to 6.5.6.3 (this section). The actual definition is 2 sentences back, hence, the reference is unneeded and distracting]

If a formal signal port is associated with an actual signal port, signal, or expression, then the formal signal port is said to be connected. If a formal variable port is associated with an actual variable port or a shared variable, then the formal variable port is said to be connected. If a formal port is instead associated with the reserved word open, then the formal is said to be unconnected. It is an error if a formal variable port is unconnected or unassociated (see 6.5.7.3). It is an error if a formal signal port of mode in is unconnected (see 6.5.6.3) or unassociated (see 6.5.7.3) unless its declaration includes a default expression (see 6.5.2). It is an error if a formal signal port of any mode other than in is unconnected or unassociated and its type is an unconstrained or partially constrained composite type. It is an error if some of the subelements of a composite formal signal port are connected and others are either unconnected or unassociated. It is an error if some of the subelements of a composite formal variable port are connected and others are either unconnected or unassociated.

6.5.7.1 General information (association lists)

47.15: [Edit: page 83, 1st paragraph ]

The For the association of signals with corresponding formal ports, association of a formal port of a given composite type with an actual of the same type is equivalent to the association of each scalar subelement of the formal with the matching subelement of the actual, provided that no conversion function or type conversion is present in either the actual part or the formal part of the association element. If a conversion function or type conversion is present, then the entire formal is considered to be associated with the entire actual.

47.16: [Edit: page 83, first sentence of paragraph 4]

If an interface element in an interface list includes a default expression for a formal generic constant, for a formal signal port of any mode other than linkage, or for a formal variable or constant parameter of mode in, or an interface subprogram default for a formal generic subprogram, then any corresponding association list need not include an association element for that interface element. For an interface element that is a formal generic constant, a formal signal port, or a formal variable or constant parameter, if the association element is not included in the association list, or if the actual is open, then the value of the default expression is used as the actual expression or signal value in an implicit association element for that interface element. For an interface element that is a formal generic subprogram, if the association element is not included in the association list, or if the actual is open, then the subprogram denoted by the formal generic subprogram is determined by the interface subprogram default as described in 6.5.6.2.

47.17: [Edit: page 83, bottom of the page, note 2]

NOTE 2-Although a default expression can appear in an interface element that declares a (local or formal) signal port, such a default expression is not interpreted as the value of an implicit association element for that port. Instead, the value of the expression is used to determine the effective value of that port during simulation if the port is left unconnected (see 14.7.3).

6.5.7.3 Port map aspects

47.18: [Edit: page 87, 1st paragraph of 6.5.7.3 ]

A port map aspect associates signals, shared variables, or values with the formal ports of a block. The following applies to both external blocks defined by design entities and to internal blocks defined by block statements.

6.5.7.3 Port map aspects

47.19: [Edit: page 88, 3st paragraph of page ]

An actual associated with a formal signal port in a port map aspect shall be a signal, an expression, or the reserved word open. An actual associated with a formal variable port in a port map aspect shall be a shared variable or a formal variable port.

8.7 External names

47.20: [Edit: page 115, Note 1 ]

NOTE 1-A generic constant may be denoted by an external constant name, and a signal port may be denoted by an external signal name, and a variable port may be denoted by an external variable name.

10.5.2.1 General

47.21: [Edit: page 151, list and paragraphs just before notes ]

- If the target is a signal port or signal parameter of mode in, a force mode of in is used.
- If the target is a signal port of mode out, inout, or buffer, or a signal parameter of mode out or inout, a force mode of out is used.
- If the target is not a signal port or a signal parameter, a force mode of in is used.

It is an error if a force mode of out is specified and the target is a signal port of mode in.

11.7.1 General

47.22: [Edit: page 151, list and paragraphs just before notes ]

A component instantiation statement defines a subcomponent of the design entity in which it appears, associates signals or values with the signal ports and shared variables with the variable ports of that subcomponent, and associates values with generics of that subcomponent. This subcomponent is one instance of a class of components defined by a corresponding component declaration, design entity, or configuration declaration.

14.3.5 Port map aspect

47.23A: [Edit: page 205, 1st paragraph through the last paragraph of 14.3.5 ]

[Comment: change text to include or exclude variables]

d) For each port association element associated with the port declaration, if the actual is not the reserved word open, the port or subelement or slice thereof designated by the formal part is then associated with the signal, shared variable, or expression designated by the actual part. This association involves a check that the restriction on port associations (see 6.5.6.3) are met. It is an error if this check fails.

47.23B:

If a given formal signal port is a port of mode in whose declaration includes a default expression, and if no association element associates a signal or expression with that port, then the default expression is evaluated and the effective and driving value of the port is set to the value of the default expression. Similarly, if a given formal signal port of mode in is associated with an expression that is globally static and the reserved word inertial does not appear in the actual part of the association element, that expression is evaluated and the effective and driving value of the port is set to the value of the expression. In the event that the value of a signal port is derived from an expression in either fashion, references to the predefined attributes 'DELAYED, 'STABLE, 'QUIET, 'EVENT, 'ACTIVE, 'LAST_EVENT, 'LAST_ACTIVE, 'LAST_VALUE, 'DRIVING, and 'DRIVING_VALUE of the port return values indicating that the port has the given driving value with no activity at any time (see 14.7.4).

47.23C:

If an actual signal is associated with a formal signal port of mode in or inout, and if the type of the formal is a scalar type, then it is an error if (after applying any conversion function or type conversion expression present in the actual part) the subtype of the actual is not compatible with the subtype of the formal. If an actual expression is associated with a formal signal port (of mode in), and if the type of the formal is a scalar type, then it is an error if the value of the expression does not belong to the subtype denoted by the subtype indication of the declaration of the formal.

47.23D:

Similarly, if an actual signal is associated with a formal signal port of mode out, inout, or buffer, and if the type of the actual is a scalar type, then it is an error if (after applying any conversion function or type conversion expression present in the formal part) the subtype of the formal is not compatible with the subtype of the actual.

47.23E:

If an actual signal or expression is associated with a formal signal port, and if the formal is of a composite subtype, then it is an error if the actual does not contain a matching element for each element of the formal. This check is made after applying the rules of 5.3.2.2 and, in the case of an actual signal, after applying any conversion function or type conversion that is present in the actual part. It is also an error if the mode of the formal signal port is in or inout and the value of each element of the actual (after applying any conversion function or type conversion present in the actual part) does not belong to the corresponding element subtype of the formal. If the formal signal port is of mode out, inout, or buffer, it is also an error if the value of each element of the formal (after applying any conversion function or type conversion present in the formal part) does not belong to the corresponding element subtype of the actual.

47.24: [Add: page 205, after last paragraph of section 14.3.5]

If an actual is associated with a formal variable port, and if the formal is a noncomposite subtype, it is an error if the subtype of the formal is not compatible with the subtype of the actual. If an actual is associated with a formal variable port, and if the formal is a composite subtype, then it is an error if the actual does not contain a matching element for each element of the formal.

47.25: [This is redundant since variables must be a PT and signals not, however, it is probably best if it is specified.]

It is an error if a shared variable is associated with a formal signal port. It is an error if a signal is associated with a formal variable port.

14.7.3.1 General

47.26: [Edit: last paragraph page 215, first of 216]

If a signal of a given composite type has a source that is of a different type (and therefore a conversion function or type conversion appears in the corresponding association element), then each scalar subelement of that signal is considered to be active if the source itself is active. Similarly, if a signal port of a given composite type is associated with a signal that is of a different type (and therefore a conversion function or type conversion appears in the corresponding association element), then each scalar subelement of that port is considered to be active if the actual signal itself is active.

47.27: [Edit: Note 2 at end of 14.7.3.1 on page 216]

NOTE 2-The rules concerning association of actuals with formals (see 6.5.7.1) imply that, if a composite signal is associated with a composite signal port of mode out, inout, or buffer, and if no conversion function or type conversion appears in either the actual or formal part of the association element, then each scalar subelement of the formal is a source of the matching subelement of the actual. In such a case, a given subelement of the actual will be active if and only if the matching subelement of the formal is active.

14.7.3.2 Driving values

47.28: [Edit: page 217, List item 2]

- If S has one source that is a signal port and S is not a resolved signal, then the driving value of S is the driving value of the formal part of the association element that associates S with that port (see 6.5.7.1). The driving value of a formal part is obtained by evaluating the formal part as follows: If no conversion function or type conversion is present in the formal part, then the driving value of the formal part is the driving value of the signal denoted by the formal designator. Otherwise, the driving value of the formal part is the value obtained by applying either the conversion function or type conversion (whichever is contained in the formal part) to the driving value of the signal denoted by the formal designator.

47.29: [Edit: page 217, Note 1]

NOTE 1-The algorithm for computing the driving value of a scalar signal S is recursive. For example, if S is a local signal appearing as an actual in a port association list whose formal signal port is of mode out or inout, the driving value of S can only be obtained after the driving value of the corresponding formal part is computed. This computation may involve multiple executions of the preceding algorithm.

47.30: [Edit: page 217, Note 3]

NOTE 3-The driving value of a port that has no source is the default value of the port (see 6.5.2).

14.7.3.3 Effective values

47.31: [Edit: page 217,first bullet point, part of list item e]

e) The effective value of S is then determined as follows: - If S is a signal declared by a signal declaration, a signal port of mode out or buffer, or an unconnected signal port of mode inout, then the effective value of S is the same as the driving value of S.

47.32: [Edit: page 218,2nd and 3rd bullet point, part of list item e]

- If S is a connected signal port of mode in or inout, then the effective value of S is the same as the effective value of the actual part of the association element that associates an actual with S (see 6.5.7.1). The effective value of an actual part is obtained by evaluating the actual part, using the effective value of the signal denoted by the actual designator in place of the actual designator.
- If S is an unconnected signal port of mode in, the effective value of S is given by the default value associated with S (see 6.4.2.3).

47.33: [Edit: page 218 ,notes 1 and 2]

NOTE 1-The algorithm for computing the effective value of a signal S is recursive. For example, if a formal signal port S of mode in corresponds to an actual A, the effective value of A shall be computed before the effective value of S can be computed. The actual A may itself appear as a formal signal port in a port association list. NOTE 2-No effective value is specified for linkage ports, since these signal ports cannot be read.

14.7.3.4 Signal update

47.34: [Edit: page 218 ,last paragraph]

A net is a collection of drivers, signals (including signal ports and implicit signals), conversion functions, and resolution functions that, taken together, determine the effective and driving values of every signal on the net.

14.7.4 Updating implicit signals

47.35: [Edit: page 220 ,2nd to last paragraph of section]

Similarly, the current value of a given interface signal denoted by R is said to depend upon the current value of an implicit signal S if R denotes a signal port of mode in and S is the actual associated with that port.

16.2.4 Predefined attributes of signals

47.36: [Edit: page 220 ,restrictions of S'DRIVING]

Restrictions: This attribute is available only from within a process, a concurrent statement with an equivalent process, or a subprogram. If the prefix denotes a signal port, it is an error if the port does not have a mode of inout, out, or buffer. It is also an error if the attribute name appears in a subprogram body that is not a declarative item contained within a process statement and the prefix is not a formal parameter of the given subprogram or of a parent of that subprogram. Finally, it is an error if the prefix denotes a subprogram formal parameter whose mode is not inout or out.

47.37: [Edit: page 220 ,restrictions of S'DRIVING_VALUE]

Restrictions: This attribute is available only from within a process, a concurrent statement with an equivalent process, or a subprogram. If the prefix denotes a signal port port, it is an error if the port does not have a mode of inout, out, or buffer. It is also an error if the attribute name appears in a subprogram body that is not a declarative item contained within a process statement and the prefix is not a formal parameter of the given subprogram or of a parent of that subprogram. Finally, it is an error if the prefix denotes a subprogram formal parameter whose mode is not inout or out, or if S'DRIVING is FALSE at the time of the evaluation of S'DRIVING_VALUE.

Comments

Topic revision: r31 - 2017-07-17 - 23:18:36 - JimLewis
 
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