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ConditionalExpressions
(2020-02-17,
JimLewis
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---+ Conditional Expressions and/or Operator %TOC% ---++ Proposal Editing Information * Who Updates: Main.CliffordWalinsky, Main.JimLewis, Main.TristanGingold, <Add YourName >, ... * Date Proposed:2014-7-28 * Date Last Updated:2014-7-28 * Priority: * Complexity: * Focus: ---++ Language Change Specification Link [[TopLCS2016_036]]: Implementation 1. [[LCS2016_036a]]: New implementation based on "when"/selected signal assignment. ---++ Requirement Summary See prior work at [[/vhdl-200x/vhdl-200x-ft/proposals/ft10A_nnary.pdf][FT10A]]. Rejected due to ambuguity introduced by the comma (","). Could use "else" instead of "," to create a general syntax. Main issue missing is conditional expressions in a declaration, otherwise, a conditional assignment is possible. Does the feature also need to work in additional contexts, such as a port map or parameter association. Can be language syntax, or a subprogram with anonymous IO. ---++ Related Issues: ---++ Current Problems / Issues ---++ Implementation 1: Language Syntax Can be implemented with language syntax using the same syntax as conditional assignment: <verbatim>constant T : time := 1 ns if gA_VAL = '1' else 10 ns ;</verbatim> No parser-generator conflicts were detected when expanding the grammar of an existing compiler with the above syntax. The expansion consists of the following additional rule: <verbatim><expression> ::= '?' '?' <primary> | <logical_expression> 'if' <expression> 'else' <logical_expression> | <logical_expression></verbatim> The change expands the definition of <expression> so that anywhere that an expression is valid, a conditional expression can also appear. -- Main.JimLewis - 2014-11-26 On comp.lang.vhdl, Allan Herriman noted that a BNF production for "conditional expressions" is already defined. Although it allows leaving out the else which implies "unaffected". <verbatim>conditional_expressions ::= expression when condition { else expression when condition } [ else expression ]</verbatim> ---++ Implementation 2: Language Syntax If for some reason, 1 is rejected, add conditional expressions to initialization of constants, signals, and variables. So add the support there: In 6.4.2.2 Constant declarations, change constant declaration to: <verbatim>constant_declaration ::= constant identifier_list : subtype_indication [ := expression | conditional_expressions ] ; </verbatim> 6.4.2.3 Signal declarations, change signal declaration to: <verbatim>signal_declaration ::= signal identifier_list : subtype_indication [ signal_kind ] [ := expression | conditional_expressions ] ; </verbatim> In 6.4.2.2 Variable declarations, change variable declaration to: <verbatim>variable_declaration ::= [ shared ] variable identifier_list : subtype_indication [ := expression | conditional_expressions ] ; </verbatim> ---++ Implementation 3: Subprograms with anonymous inputs Can be implemented as a function that uses anonymous inputs: <verbatim>constant T : time := Cond(gA_VAL = '1', 1 ns , 20 ns) ; ... function Cond ( Sel : boolean ; A : anonymous ; B : A'Subtype ) return A'subtype ; function Cond ( Sel : bit ; A : anonymous ; B : A'Subtype ) return A'subtype ; function Cond ( Sel : std_ulogic ; A : anonymous ; B : A'Subtype ) return A'subtype ; </verbatim> ---++ Questions ---++ Proposal For the record, conditional expressions were added in Ada 2012: http://www.ada-auth.org/standards/12rm/html/RM-4-5-7.html ---++ General Comments -- Main.ErnstChristen - 2015-01-21 This capability is often required in initial value expressions. The workaround with a function call is clumsy. ---++ Supporters _Add your signature here to indicate your support for the proposal_ * Main.CliffordWalinsky (in favor of expanding the VHDL grammar, not in favor of implementation through anonymous types). * -- Main.JimLewis - 2014-12-04 * -- Main.ErnstChristen - 2015-01-21 * -- Main.PatrickLehmann - 2016-02-18 * -- Main.ThomasPreusser - 2016-11-06 (using existing *when* syntax in initializer context) ---++ In opposition _Add your signature here to indicate your opposition to the proposal_ *
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Topic revision: r17 - 2020-02-17 - 15:34:28 -
JimLewis
P1076
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