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<!-- * Set ALLOWTOPICCHANGE = P1076AdminGroup --> ---+!! P1076 May 15, 2014 Meeting Minutes ---++!! Attendees: * Main.PeterFlake * Main.JimLewis * Main.CliffordWalinsky * Main.RyanHinton * Main.StevenDovich * Main.DavidBishop ---++!! Agenda: %TOC% ---++ Group Action Item List * All: Final Review of [[IeeeVHDL2008Lists][IEEE 2008 Remaining Items List]] and [[AccelleraVHDL2008Lists][Accellera 2008 Remaining Items List]] * All: Rank Proposals * All: Review Proposals ---++ Action Item Review *Marked completed before meeting* * 2034 - Linked into clocked short hand [[ClockedShorthand]] * 2035 - Linked into clocked short hand [[ClockedShorthand]] * 2041 - Linked into [[Partiallyconnectedvectorsonportmap]] * Bugzilla 293 - link into [[AlternatePathName]] * Bugzilla 283 - Resolved as Invalid *Check status during meeting* * Open - revive 1076.6 to handle syntheis proposals on collected requirements page [[MeetingAugust25]] [[MeetingAugust11]] * [[SynthesisAttributes][Synthesis Attributes]] - Package of attributes in 1076? * Brent suggested that 1076.6 be subsumed into the 1076 * Meeting attendees suggest add this as an informative annex to 1076 if it can be ready on time * Ryan: Arbitrary width real: see [[2012_MeetingNovember8][Nov 8 2012 meeting]] * Open - Multi dimensional Array restructuring: Array <--> Matrix Transformations [[2012_MeetingJuly19]] [[MeetingDecember15]] * Matlab has built-in reshape functions * In VHDL - explicit vs implicit defined operator * David Bishop: Requiring an implicit operator could delay implementations * Can this be handled by anonymous types on interfaces or generics on a package? * Language facility for creating implicit operators? * Ryan - Slicing Multidimensional Arrays (FT15) maybe related to above [[2012_MeetingMay24]] * David Bishop: Bugzilla 17 - add_carry in numeric_std as well as fixed/floating packages * In the fixed point package, but not floating point package. * Not in numeric_std. Add for consistency? * David Bishop: Bugzilla 15 - Should numeric_bit/std have resize with size_res parameter? * David proposed it for consistency with the fixed and floating point packages * David Bishop - 262 - Fixed Generic Pkg and checking valid range * [[DeferredSharedVariables][Done]] Cliff - 2119 - declare a protected type and object of that type in a single package * Peter - 2012 - Wants to remove the priority from if-elsif-elsif structures under some conditions. Proposes: "if elsor elsor". * [[http://www.eda.org/twiki/bin/view.cgi/P1076/UniqueCondition][UniqueCondition]] * Done: Jim - find examples from OP * Work in progress - still more to do. *Not Reviewed during meeting* * Jim - Fork and Join [[2012_MeetingJune21]] * Original Verilog, simple fork and join - not used much. Hence, not much value in implementing a simple mechanism * SV - more complicated and have ability to kill later * Add template proposal and move to "not now" list * Jim - Mark bugzillas for which we have a proposal with that status * Jim - Table driven modeling via protected types [[2012_MeetingMay10]] * David Koontz - Simulation Controls [[MeetingAugust11]] * Open - IR 2108 - Level sensitive check - A "wait" that checks condition before stopping * Cliff - Look into passing an expression to a input signal parameter (2008 allows this for an input signal port) * Jim - 2109 - Requests semaphore implementation via a protected type * Requires wait inside of a protected type * ?Requires signal inside of a protected type? * Also interested in a resolution function based semaphore implementation * Jim - 2113 - Init ROM / Array data structure using file read * Add textio read to 1076.6 list * Add open source family of read array functions to initialize RAM/ROM * Jim - 2125 - Resolving 'Z' and '-' results in 'X" rather than '-' * Jim - 2003 - simulating and synthesizing multi-cycle paths * Waveform assignment (multiple after) would be appropriate here, if a synthesis tool can handle it. * OPEN - 2026 - Upward propagating Generics. * Would an external name reference to a constant accomplish some of the intent here? * An "OUT" generic would need to have similar constraints to the external name usage. * One use models: Out generic of one design connecting to in generic of another. * Need other use models * OPEN - 2033 - Increment operator with modulo wrap around. * One Option: Does ADA do something like this? Can it be done as a subtype constraint? * Another Option: Add inc / dec packages or to standard packages? ---++ Quick Review of IEEE and Accellera Remaining Items Lists * See: [[IeeeVHDL2008Lists][IEEE 2008 Remaining Items List]] and [[AccelleraVHDL2008Lists][Accellera 2008 Remaining Items List]] ---++ Initial Rank of Proposals Collected Requirements List * Probably will not get here in this meeting ---++ Review Proposals Collected Requirements List * Probably will not get here in this meeting ---++ Update Rank of Proposals Collected Requirements List * Probably will not get here in this meeting ---++ Review and Approve Meeting Minutes: * Motion: Ryan 2nd:Cliff ---++ Next Meeting: [[2014_MeetingMay29][Thursday May 29, 2014]] 8 am Pacific ---+++ Previous Meeting: [[2014_MeetingMay1][Thursday May 1, 2014]]
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Topic revision: r3 - 2020-02-17 - 15:36:14 -
JimLewis
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