P1076 March 7, 2013 Meeting Minutes

Attendees:

Agenda:

P1735 Encryption

  • Need some clarification on specification of public key
  • Looking to share with our group and get buy in

Accellera TC Remaining Items

  • Env 1 & 4
    • Cliff wonders if Env 4 should be rejected. Jerry and Peter think it should be considered.
  • ENV 10: VCD for VHDL
    • Mapping of VHDL data types
    • DPI may help clarify this
    • Could reference SystemVerilog clause 21.7
    • What is the point of this?
    • Ext tools processing VHDL
    • Package with VHPI to do this?
    • Value? Not necessarily a huge use for it.
    • Table for now. Come back to it.
  • ENV 11: Multiple Hierarchy Roots
    • Used in SV
    • Use model in VHDL?
    • Connect things with external references
    • AI: Jerry write something up
  • ENV 12: Standardized logical to physical library mapping
    • Reject
    • Libraries are designed to be logical
    • If you cannot create physical libs, why create a mapping?
  • DTA 2: Integers > 32 bits
    • Need proposal for this. Have talked about it before
    • Integer support arbitrary range
    • Create a set of standard subtypes (32 bit, 64 bit)
    • AI: Martin and Ryan to work on proposal
    • AI: Cliff create competing implementation for long integer
  • DTA 4: Variant Records/Unions
    • Have proposal template with initial thoughts

Action Items:

  • Env 11: AI: Jerry write something up
  • DTA 2: AI: Martin and Ryan to work on proposal
  • DTA 2: AI: Cliff create competing implementation for long integer

Review and Approve Meeting Minutes:

  • Motion: Jerry 2nd: Ryan

Next Meeting Date (proposed):

Thursday March 28, 8 am Pacific (Note: US Daylight savings time)

Topic revision: r3 - 2020-02-17 - 15:36:12 - JimLewis
 
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