1076.1 WG Meeting ================= 6/17/2005, Anaheim Hilton Attendees --------- Peter Ashenden, Ashenden Designs, DASC chair * Ken Bakalar, Mentor Graphics Dave Barton, EDAptive Computing * Ernst Christen, Synopsys, 1076.1 vice-chair * Deepika Devarajan, Ansoft Corp. Sameer Khir, Ansoft Corp. Michael Mirmak, Intel Corp. John Shields, Mentor Graphics Thuy NT Tran, Pyrotest John Willis, FTL Systems (part time) Alex Zamfirescu, ASC Systems * * present in person Agenda ------ 1. Working Group status update 2. IBIS Presentation 3. VHDL-AMS language direction 4. Tentative meeting schedule 5. Other business Ernst opened the meeting at 1:35 pm PDT. Peter showed the slides related to the IEEE patent policy, and the opportunity was given to announce relevant patents. None was presented. 1. WG status update ------------------- See meeting slides #3 through #7 Based on information from the DASC meeting the same morning, Ernst mentioned the delay of the VHDL 200x effort and suggested that we may have to adjust our goals as to the basis of 1076.1-2005. John Shields and Deepika expressed concern over the 200x delay, and John suggested to include at least the changes related to the architecture body and the purity of now. Details are to be worked out. With regards to 1076.1.1, the standard can be purchased from the IEEE as of 6/17/2005. 2. IBIS Presentation -------------------- See meeting slide #8 and Michael Mirmak's slides Michael Mirmak gave an overview of the IBIS organization, which manages IBIS and ICM (IBIS InterConnect Modeling) and IBIS (I/O Buffer Interface Specification). IBIS is a universal standard describing the analog behavior of digital device buffers. An example are I/V curves at the interfaces of a model. The model itself is a black box. There are a small number of tools available that support IBIS with language interoperability (VHDL-AMS, Verilog-AMS, SPICE). The IBIS 4.0 cook book will be released next month. Suggestions from the IBIS organization: - table lookup functions - evaluation of strings passed as generics. One use of this is to pass the name of a function to call into a model. - translators between languages Ken acknowledged the first two requirements, but suggested that language translators are not likely to come from major vendors. He suggested that an alternative would be a library of primitives that is standardized. Ernst mentioned a discussion he had with Bob Ross about language translation and suggested that purely analog behavior could probably be translated, but that the odds are slim when it comes to mixed signal behavior as VHDL-AMS and Verilog-AMS use different approaches. He suggested that some of the IBIS requirements related to a library of primitives could possible by handled by a Recommended Practices standard. Michael, mentioned a presentation by Arpad Muranyi to the IBIS summit earlier the same week about "IBIS 4.1 Macros for Simulator Independent Models". The presentation can be found at http://www.eda-twiki.org/ibis/summits/jun05/muranyi.pdf. With regards to the status of Verilog-AMS, Ken remarked that Verilog-AMS 2.2 is based on IEEE Std. 1364-1995, with some extensions from 1364-2001. Verilog-AMS 2.3 has been abandoned in favor of SystemVerilog-AMS. Ken stated that supporting 2.2 is difficult because of the 1995 legacy. A conclusion was reached that it is important to support primitives that are portable across tools and languages. 3. VHDL-AMS language direction ------------------------------ See meeting slides #9 through #12 With regards to XMR, Ken remarked that its purpose is to instrument models, in particular test benches. Verilog supports XMR, but any Verilog model that uses XMR is asking for trouble. There should really be a distinction between models and test benches. Peter and John Shields explain the more restrictive package based approach discussed by VHDL 200x. Ken said Mentor Graphics has something similar for analog. Ken and Dave expressed interest to see the work on conversion models As additional focus areas, the following were suggested: - IP protection (Deepika). The VHDL proposal is sufficient, but what is its status - Symbol format (Deepika). This is an important issue for VDA and SAE - Table data types (Deepika). This appears to be related to the IBIS suggestions - Vector/matrix arithmetic (Ernst) to support vector quantities. Dave suggested that this may be a topic to be addressed by the Numerics effort headed by Alex - Temperature relaxation models (Alex) 4. Tentative meeting schedule ----------------------------- See meeting slide #13 5. Other business ----------------- None. Ernst adjourned the meeting at 3:20 pm PDT.