IEEE P1076.1 Discussion about the Current Language Revision

Dear member at large of the P1076.1 Working Group,

 

At its past two meetings the active WG members have reviewed the status of
the ongoing revision of IEEE Std 1076.1-2007 and put it in perspective with
the time we have available to complete the language revision. Our PAR
(Project Authorization Request) will expire on December 31, 2015, and with a
lead time of at least 9 months to hold a ballot, the mandatory ballot
resolution and the more than likely recirculation ballot this gives us at
most 12 months to complete the definitional work. Even though it is possible
to extend the PAR, the time is still tight, particularly if something slips.

 

We have come up with the following proposal that the active contributors
believe to be able to complete in the available time and with the available
resources.

 

We propose to complete the following projects for this revision of the
language:

.         Update the language definition to become a superset of IEEE Std
1076-2008. This will bring significant functionality to VHDL-AMS, but will
take a considerable amount of work to enhance the VHDL-AMS definition to
become aligned with the extensive new functionality in the 2008 revision of
VHDL.  We expect this work, together with the related LRM work, to have a
duration of about a year.

.         Extension of VHPI to provide minimal support for VHDL-AMS
concepts. This work will include traversal of an uninstantiated design unit
and of an elaborated model. We have no plans to provide simulation control
at this time. This work is scheduled to last till December of this year.

.         Integration of IEEE Std 1076.1.1-2011 into P1076.1-201x. The plan
calls for a completion of this project in August of this year.

.         Table driven modeling. A strawman implementation is available, but
there are several open issues that await resolution. Current expectation is
to complete this work by November 2014.

.         Vector/matrix operations. We also have a strawman implementation,
and completion is anticipated in the September/October time frame.

.         Frequency-domain modeling. This project has been completed, but a
review will be required, which should take about a month.

.         Updating the LRM to include the new functionality defined by these
projects. A preliminary plan anticipates to complete this work in March of
next year.

 

In addition we propose to drop the following three projects from this
revision:

.         Mixed netlists. This project aimed at supporting a port
association where the formal and actual were different objects, e.g. a
terminal and a signal, by defining rules to insert instances of conversion
units that would implement the necessary semantics to pass a value between
the actual and formal. We believe that this project would require an effort
exceeding one year, for which we do not have the resources.

.         Support for partial differential equations. The champion for this
project has recently become unavailable, and we do not have a plan for its
completion.

.         Support for a limited dimensional analysis capability in VHDL-AMS.
The intended functionality isn't as powerful as we would like it to be
without also supporting mixed netlists.

 

Since this proposal marks a departure from earlier communications I believe
that the Working Group should have a chance to provide feedback to the
active contributors. I am opening this proposal for a discussion on the
reflector starting Tuesday, April 1 and ending Tuesday, April 15. The
discussion will be followed by an email vote by the Working Group to approve
the proposal or a revised version of it. I am particularly interested to
hear from end users of the language to understand the impact this proposal
may have on their work. At the same time I would like to encourage your
active participation in the work of the Working Group to complete these
projects on time.

 

To participate in the discussion please respond to this email. 

 

Ernst Christen

Chair, IEEE P1076.1 Working Group


-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.





To unsubscribe to the vhdl-ams mailing list:
mailto:Majordomo@eda.org?subject=Unsubscribe&body=unsubscribe%20vhdl-ams