Hi,
If you believe your IP is valuable and that making it available as
source code compromises that value, you need a delivery mechanism that
keeps the source code from being inspected while allowing it to be
used. A compiled model does provide that protection or at least some
of it. For every tool in a user's production flow that has to work
with that model you need to provide the model compiled for that purpose
(if that is possible). Not every tool will have a persistent compiled
representation suitable for delivery. If you do not wish to dictate
what tools a customer may use, you will have to delivery ( and
qualify/certify ) your model with all tools. That is expensive for the
IP provider; it can become a logistical nightmare, too. And, the
protection may be compromised at runtime by tool features, such as
debugging and code understanding mechanisms. After all, the tool is
just working with a compiled model; it does not know that there is any
intent to protect it.
If I can speak about the IP protection model proposed for VHDL, it is
applied at the lexical level to HDL source code. The text is annotated
to identify what text is to be encrypted and what specific encryption
mechanisms are chosen to be used. An encryption tool(likely a VHDL
compiler but it could be a standalone utility) processes the text and
produces a text file in which that region of text is replaced by an
encrypted, encoded block and the remainder of the HDL is clear text.
This can be delivered to any user appropriate to your business
purpose. The user may use this IP in any tools that are capable of
decrypting that IP. Without going into details about the various
mechanisms of secret or public key encryption choices available, there
is a great deal of control the IP provider has in enabling only a
selected set of tools or users to use his/her IP.
A further aspect of this mechanism is that the tool is obligated to
protect the information model of the IP and not reveal any information
that could compromise the IP while providing its intended purpose.
The IP is opaque to debuggers, browsers, etc., except as required to
use the model with the tool. There is a mechanism for the IP provider
to define a viewport to makes certain aspects of the model visible to
the user. For digital VHDL models, the semantics of what aspects of the
model are protected have a foundation. For AMS models, this would be
an area for semantic definition.
The IP protection mechanism is expected to become part of the VHDL
standard and conforming tools will have a solid basis for IP providers
to deliver portable models that will be protected. It is expected to
part of both Verilog and VHDL standards and should be highly
leveragable technology for tool providers. The document that Ernst
refers to is a overview powerpoint presentation. I don't know if the
draft specs from Accellera can be made available to this group, but I
can explore it if there is interest.
It might be a bit premature until this group is ready to propose and
work on new 1076.1 features. The Verilog spec is in the latest 1364,
annex H. The VHDL specs are much more comprehensive in terms of
details and use cases. You may expect to see it in an Accellera
version of 1076 later this Fall.
Regards, John Shields
holmes wrote:
Hello,
From a model
delivery and IP protection
standpoint, how is an encrypted VHDL-AMS model different from (or
better than) a
compiled VHDL-AMS model? Doesn’t customer have to compile the
encrypted model anyway?
Regards,
Jim Holmes
I'd like the reply you draft below. Thank
you very much for the
information you lead us to for a reviewing.
Arpad, you are agreeing with me that Ernst is
very good, are not you?
Hi
Arpad,
Encryption is a topic that comes up from time to time. The issue is not
specific to
VHDL-AMS, but affects also VHDL (IEEE Std 1076). A proposal has been
submitted
to the VHDL
Analysis and Standardization Group (VASG) to support encryption in a
VHDL text.
You can
find some information about the topic by following the VHDL-200x link
under
P1076 at
eda.org. Go to Old VHDL-FT documents, near the bottom there are links
to
relevant
documents. There is also a presentation at
http://www.accellera.org/apps/group_public/download.php/118/VHDL_IP_Encryption.ppt.
Thanks.
Ernst Christen
On Mon, 24 Apr 2006 11:25:32 -0700, Muranyi, Arpad wrote:
> Hello everyone,
>
> Sorry for bringing up such off topic questions all the time,
> but I would like to find out whether encryption has been
> considered by the workgroup for VHDL-AMS models.
>
> The reason I am asking is because this has been brought up
> in the recent IBIS Open Forum discussions in connection
> with modeling bleeding edge high speed buffers behaviorally.
> Semiconductor vendors feel increasingly uneasy about
> releasing even behavioral models for such buffers without
> encryption. In addition we do not like the idea of using
> the individual and proprietary encryption schemes of EDA
> vendors, because that would require the model makers to
> encrypt the same model multiple times for each tool. It
> seems that there is a strong need for some sort of a tool
> independent encryption scheme.
>
> We thought we should look around what has been done, if
> anything, before we reinventing the wheel.
>
> Thanks,
>
> Arpad
> =============================================================
Thuy NT
Tran
Project Manager, Jr
www.pyrotest.com
Received on Tue Apr 25 09:59:18 2006