Unreachable Grammar

Dear VHDL-AMS Working Group,
in the VHDL-AMS Syntax is the element

object_declaration :=
constant_declaration | signal_declaration | variable_declaration | 
file_declaration | terminal_declaration | quantity_declaration

This element can only be reached via the "declaration" element, but 
there is no way to reach "declaration", if beginning from design_file.

I read through the description of the IEEE Standard, but there 
"declaration" was only mentioned on page 50 , and not declared further. 
I assume, that "declaration" is something like an abstract superclass of 
all kinds of declarations, but if it is that case, why is "declaration" 
and "object_declaration" mentioned in the syntax?
It would be helpful if somebody could clarify the intentions behind 
these elements.
Yours Sincerely,
    Thilo Brause