Subject: Request for Q'Above(E) clarification
From: Ernst Christen (christen@analogy.com)
Date: Fri Sep 29 2000 - 10:12:56 PDT
Tim,
The LRM defines implicit signals of the form Q'Avove(E) to be of type
BOOLEAN. Hence they are unresolved and can only have one driver.
According to 12.6.6 the drivers for all such implicit signals are
assigned to by the analog solver. In essence, this corresponds to your
interpretation A, with the exception that the LRM is silent about the
number of such signals because a model cannot detect whether several
textual occurrences of Q'Above(E) refer to the same signal or to
different signals.
Your point about potentially misleading models with this definition is
well taken. However, the text of your example is only misleading for
somebody who doesn't understand the semantics. This is not unlike
sequential signal assignments of the form
s1 <= expression;
s2 <= s1;
which as you may know yield a result that is at least surprising to
novices until they understand the semantics.
The modeling guideline that can be derived from the semantics is that
a discontinuity in the expression Q-E obtained from Q'Above(E) must be
treated the same as a discontinuity in any quantity. In essence,
Q'Above(E) is a syntactic shorthand defined for convenience; an
alternative approach would have been to define an implicit signal
QE'AboveZero with semantics that are otherwise similar to those of
Q'Above(E). Then, the user would have to define a simple simultaneous
statement QE == Q - E; to get the desired behavior. One small
difference: in the alternative approach E could not contain a primary
that is a variable.
Please let me know if I can be of any more help in this matter.
Ernst Christen
Tim McBrayer writes:
> Please forgive me if this appears on the VHDL-AMS mailing list twice: I
> sent this some time back and it apparently never made it to the list.
>
>
> To the VHDL-AMS 1076.1 Working Group:
>
> My colleagues and I have been having a disagreement over the precise
> definition of the implicit signal Q'above(E) in VHDL-AMS. I was hoping
> that we could receive some clarification on this matter. Here are the two
> interpretations.
>
>
> Interpretation A:
>
> This interpretation follows a strict, LRM-based understanding. Each
> textual occurrence of the form Q'Above(E) causes the instantiation of one
> implicit signal.
>
> In this interpretation, all implicit signals Q'Above(E) are unresolved,
> and thus have only one driver, which is assigned to solely by the analog
> solver. When the value of Q'Above(E) is read in a process body, the value
> of the implicit signal is read. No attempt is made to evaluate E or
> compare it to the value of Q.
>
> This interpretation leads to potentially misleading VHDL code. Take the
> following code fragment. In it, assume Q is 1.0, E is 0.0, and Q'Above(E)
> is TRUE when the wait statement resumes.
>
> misleading: process
> variable E: real := 0.0;
> variable B: boolean := FALSE;
> begin
> <...>
> wait for 100 ns;
> E := 2.0;
> B := Q'Above(E);
> <...>
> end process misleading;
>
> In this interpretation, the boolean variable B will be assigned the value
> of TRUE, as this is the value stored in the implicit signal Q'Above(E).
> Note, however, that when the assignment to B is executed, Q is not
> actually "Above E"; that is, Q < E during the assignment to B. This is
> the source of the difference of opinion.
>
>
>
> Interpretation B:
>
>
> This interpretation is very similar in that it too implements one signal
> for each textual occurrence of the form Q'Above(E), as a single-driver,
> unresolved signal. The difference comes when the value of this signal is
> read.
>
> At process execution time, instead of reading the value of the implicit
> signal Q'Above(E) as stored in the kernel, the boolean value (Q > E) is
> recomputed upon execution of the relevant code. This will take into
> account any changes to values used in the computation of the value of the
> expression E. With the example above, this interpretation will recompute
> (Q > E) with quantity Q = 1.0 and variable E = 2.0 . With these values,
> (Q > E) is FALSE, so the assignment to B will cause B to have the value
> FALSE.
>
> This interpretation has the benefit that the sequential statement:
>
> B := Q'Above(E);
>
> does what seems logical; that is, at the moment of execution, B is
> assigned (Q > E). However, is does not adhere to strict VHDL signal
> semantics. The value of the implicit signal becomes more or less
> unused, and the signal is only used for event information, triggering
> wait statement resumption and such.
>
>
>
> The question, of course, is which interpretation is correct according to
> the intent of the 1076.1 LRM. Thank you for considering this matter.
>
> Best regards,
> --
> Tim McBrayer (508) 303-5333
> Principal Software Engineer e-mail me for my PGP key
> Innoveda Inc. tmcbrayer@innoveda.com
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