Subject: RE: Checking for dimensional consistency in VHDL-AMS models
From: Bakalar, Kenneth (Kenneth_Bakalar@mentorg.com)
Date: Wed Dec 22 1999 - 08:10:18 PST
Eduard,
Why do you not declare and use different natures for sets of incompatible
ports? What additional characteristics of the port are encoded in the
attribute?
Ken Bakalar
-----Original Message-----
From: Eduard Moser [mailto:moser@fli.sh.bosch.de]
Sent: Wednesday, December 22, 1999 4:30 AM
To: vhdl-ams@eda.org
Subject: Re: Checking for dimensional consistency in VHDL-AMS models
I just want to add a minor remarks to the ongoing discussion about
dimensional checking.
If somebody comes up with a general concept for dimensional
calculation and consistency checking that is certainly something worth
to consider. But I assume due to the lacking support within the base
language VHDL it will take a long time and presumably it will not help
anybody prior to 2005.
Our requirements on dimensional consistency are less exciting than the
proposed solutions. We only want to check correct port mapping for
component instantiation.
Ernst writes:
...
> The issue has not been further considered till now. Note, however,
> that annotation of units is possible with user-defined attributes.
We use a simple user-defined attribute for each port. The user has to
take care about the consistency within the (behavioural)
architectures. Our schematic entry tool performs the consistency
checking of the port mapping (the checking is done each time a
connection is drawn, the unit of the node is determined by the
ports of the connecting components).
Eduard Moser
--Robert Bosch GmbH Tel: +49-711-811-6924 FV/FLI, Postfach 10 60 50 Fax: +49-711-811-7602 70049 Stuttgart, Germany E-mail: moser@fli.sh.bosch.de
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