Subject: Re: Checking for dimensional consistency in VHDL-AMS models
From: Mark Zwolinski (mz@ecs.soton.ac.uk)
Date: Tue Dec 21 1999 - 02:48:06 PST
David Barton wrote:
>
> Mark Zwolinski writes:
>
> At compile time, the VHDL-AMS compiler can extract the dimensions
> of each variable (or signal or quantity) in an
> expression. Constants would have to be declared to be of the
> appropriate subtype, or cast to the correct type. Similarly, "now"
> would have to be written as "(RealTime)now".
>
> Comments?
>
> Well, it depends on what you are trying to do. You have written a
> package with which you can model dimensions. You have left unsead how
> those dimensions are to be attached to each object (attributes?), how
> the VHDL-AMS compiler can "extract" them, and how the various subtypes
> can be related.
>
Dave,
The one thing I was not suggesting doing at this stage was to change
VHDL! My suggestion (and it's no more than a suggestion) is that IF a
package such as the one I posted were defined and IF users were willing
to stick to the discipline of writing models using such subtypes, then
it would be relatively simple for a parser to extract the dimension
attribute for each variable or quantity and to perform a dimensionality
check. I have discussed this briefly with a compiler writer. We don't
reckon it's a major problem. This could be implemented in a matter of
weeks (well, months). A change to VHDL will take years!
-- =================================================================== Dr Mark Zwolinski Electronic System Design Group Tel. (+44) (0)23 8059 3528 Dept. of Electronics & Computer Science Fax. (+44) (0)23 8059 2901 University of Southampton Email. mz@ecs.soton.ac.uk Southampton SO17 1BJ, UK http://www.ecs.soton.ac.uk/~mz
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