Subject: Re: Checking for dimensional consistency in VHDL-AMS models
From: Mark Zwolinski (mz@ecs.soton.ac.uk)
Date: Mon Dec 20 1999 - 10:05:11 PST
Mark Zwolinski wrote:
>
> Joe Gwinn wrote:
> >
> > Some years ago, during the development of the VHDL-AMS standard, there was
> > a desire to build into the VHDL-AMS language some kind of type-checking
> > mechanism to detect inconsistent use of dimensions (meters, seconds, m/s,
> > newtons, amps, etc) in the user-written equations describing the system
> > being modeled. At the time, dimensional checking was voted down, on the
> > theory that we didn't know how to do such a thing, and so didn't know how
> > to write the VHDL-AMS to implement such consistency checking.
> >
Following on from Joe's post and my response on Friday, I though about
this a little more. I don't think VHDL(-AMS), as it stands, has the
capability to code compile-time dimension checking in the language. I'm
not certain, indeed, that this is desirable. VHDL-AMS is a hardware
description language NOT a general programming language and environment.
Therefore things that have to be engineered from scratch in C++ can be
built in to a VHDL-AMS compiler.
With this in mind, and "borrowing" from the Los Alamos C++ library,
here's a tentative idea for including dimension checking in VHDL-AMS.
The dimensions of a subtype are expressed in powers of the seven base
dimensions: length, mass, time, current, temperature, amount of
substance and luminous intensity. Each subtype has an attribute that is
an array of powers of these 7 dimensions.
An example package is given here:
package dimensions is
type dim_array is array(1 to 7) of integer range -32 to 31;
attribute dimension: dim_array;
-- Base dimensions m kg s
A K mol cd
subtype Dimensionless is real;
attribute dimension of Dimensionless: subtype is ( 0, 0, 0,
0, 0, 0, 0);
subtype Length is real;
attribute dimension of Length: subtype is ( 1, 0, 0,
0, 0, 0, 0);
subtype Mass is real;
attribute dimension of Mass: subtype is ( 0, 1, 0,
0, 0, 0, 0);
subtype RealTime is real;
attribute dimension of RealTime: subtype is ( 0, 0, 1,
0, 0, 0, 0);
subtype Current is real;
attribute dimension of Current: subtype is ( 0, 0, 0,
1, 0, 0, 0);
subtype Temperature is real;
attribute dimension of Temperature: subtype is ( 0, 0, 0,
0, 1, 0, 0);
subtype AmountOfSubstance is real;
attribute dimension of AmountOfSubstance: subtype is ( 0, 0, 0,
0, 0, 1, 0);
subtype LuminousIntensity is real;
attribute dimension of LuminousIntensity: subtype is ( 0, 0, 0,
0, 0, 0, 1);
-- Electrical dimensions
subtype Charge is real;
attribute dimension of Charge: subtype is ( 0, 0, 1,
1, 0, 0, 0);
subtype Voltage is real;
attribute dimension of Voltage: subtype is ( 2, 1, -3,
-1, 0, 0, 0);
subtype Resistance is real;
attribute dimension of Resistance: subtype is ( 2, 1, -3,
-2, 0, 0, 0);
subtype Inductance is real;
attribute dimension of Inductance: subtype is ( 2, 1, -2,
-2, 0, 0, 0);
subtype Capacitance is real;
attribute dimension of Capacitance: subtype is ( -2, -1, 4,
2, 0, 0, 0);
end package dimensions;
At compile time, the VHDL-AMS compiler can extract the dimensions of
each variable (or signal or quantity) in an expression. Constants would
have to be declared to be of the appropriate subtype, or cast to the
correct type. Similarly, "now" would have to be written as
"(RealTime)now".
Comments?
Mark
-- =================================================================== Dr Mark Zwolinski Electronic System Design Group Tel. (+44) (0)23 8059 3528 Dept. of Electronics & Computer Science Fax. (+44) (0)23 8059 2901 University of Southampton Email. mz@ecs.soton.ac.uk Southampton SO17 1BJ, UK http://www.ecs.soton.ac.uk/~mz
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