Initialization and DC Simulation in VHDL 1076.1

Table of Contents

• 1. Introduction
• 2. VHDL 1076.1 Initialization, Quiescent State and Discontinuity Handling
  • 2.1 Domain Signal
  • 2.2 Equations Solved by the Analog Solver
  • 2.3 Initialization
  • 2.4 Mixed-Mode Simulation Cycle
  • 2.5 Break Statement
  • 2.6 Handling of Discontinuities
• 3. Rationale
  • 3.1 DOMAIN signal
  • 3.2 Equations Solved by the Analog Solver
  • 3.3 Initialization
  • 3.4 Finding the Quiescent State
  • 3.5 Handling of Discontinuities
• 4. Initialization of DAEs
  • 4.1 Theoretical Background
  • 4.2 DC Operating Point
  • 4.3 User-Specified Initial Conditions
    • 4.3.1 Why Initial Conditions
    • 4.3.2 Forms of Initial Conditions
  • 4.4 Multiple Solutions
• 5. Alternatives Considered
  • 5.1 Boolean Signal QUIESCENT and Impure Function DOMAIN
  • 5.2 QUIESCENT Indicates no A/D and D/A Interaction
  • 5.3 Dominique Rodriguez' proposal for initialization
    • 5.3.1 Dominique's Comments
    • 5.3.2 Compatibility with digital models
    • 5.3.3 Properties
  • 5.4 Discontinuity Handling
• 6. References
• Revision History