Subject: FW: [vhdl-200x] Re: TBV2: Associative arrays proposal submitted
From: Jayaram Bhasker (JBhasker@esilicon.com)
Date: Mon Apr 28 2003 - 09:11:36 PDT
Somewhere along in this discussion, the train got derailed onto the vhdl-200x track. I am
trying to set it back to the vhdl-200x-tbv track ... choo ... choo
- bhasker
------
J. Bhasker, eSilicon Corp
1605 N. Cedar Crest Blvd, Ste 615, Allentown, PA 18104
jbhasker@esilicon.com, 610.439.6831, 610.770.9634(fax)
-----Original Message-----
From: Stephen Bailey [mailto:SBailey@Model.com]
Sent: Monday, April 28, 2003 11:03 AM
To: 'Jim Lewis'; vhdl-200x
Subject: RE: [vhdl-200x] Re: TBV2: Associative arrays proposal submitted
The address bus is typically modeled as a bit vector and not as an integer value. The conversion must be performed. What is the value of requiring the user to write to_integer()? It doesn't take care of the X in the address vector problem. That problem still exists.
We should provide support for vectors as the index because this is how people model. It makes it easier and quicker to write the models. We should have an identified behavior for the X situation this is logical and reasonable (from a modeling/hardware behavior perspective).
-Steve Bailey
> Why address in bit/std_logic? To address in integer
> all that is required is a call to to_integer?
> So the to_integer would be built into the call.
> What happens when address = "X" for write and
> for read? Write invalidate all entries?
> Read, readback an "X"?
>
> Jim
>
> Stephen Bailey wrote:
> >>Is an associative array the same as the sparse array (TBV12)?
> >>I think a sparse array was intended for creating space
> >>on demand for modeling something like a RAM. Sounds
> >>like associative array is the same thing.
> >
> >
> > Associative arrays could be used to model sparse arrays.
> However, sparse arrays are more specific. They are used
> specifically for
> > modeling large memories efficiently when only a small
> percentage of the memory addresses are used in any given simulation.
> >
> > To easily model sparse memories, associative arrays would
> need to support:
> >
> > 1. A bit (std_logic) vector as an index expression.
> (The memory address.)
> > 2. Support constraining the index according to the memory size.
> >
> > I had requested that the proposal ensure that both of these
> be covered (permitted).
> >
> > There may also be efficiency of implementation
> considerations that might determine that sparse arrays should
> either have their own
> > syntax or that a standard "generic" associative array
> subtype be defined to be used for sparse array/memory
> modeling. Either of
> > these would then be what implementations key on to kick in
> any relevant optimizations.
> >
> > BTW, it would also be good to define load and dump
> operations for associative/sparse arrays.
> >
> > -Steve Bailey
> >
> >
> >
>
>
This archive was generated by hypermail 2b28 : Mon Apr 28 2003 - 09:13:39 PDT