IEEE 200X Performance Change Proposal

ID:	  PERF-07

Proposer:     John Ries
email:        johnr@model.com

Status:       Open
Proposed:     05-May-2003
Analyzed:     
Resolved:     

Enhancement Summary:     Zero-delay ordering of signals
Related issues:          PERF-01
Relevant LRM section:    12.6

Enhancement Detail:
----------------------------
When attempting to do zero-delay RTL simulation the user
is require to order clock signals changes so that flip-flops
evaluate only after the data lines have settled.  With
the current simulation semantics, the user is required to
insert zero-delay buffers to control this ordering.  This
is error prone. Changes in other parts of the design could add
or remove deltas, cause clocks to trigger to so or data to
arrive to late. Assertion languages like PSL also need to know
when the design is stable for sampling data.


Analysis:
----------------------------
[To be performed by the 200X Performance Working Group]


Resolution:
----------------------------
[To be performed by the 200X Performance Working Group]