Subject: [vhdl-200x-perf] Optimizing delta cycles
From: Jim Lewis (Jim@SynthWorks.com)
Date: Tue Dec 09 2003 - 14:31:09 PST
A few thoughts on PERF04, PERF01, and PERF07:
PERF04, PERF01 seem to be about optimizing away delta cycles
to achieve faster simulations.
First thought is that we are not allowed to introduce race
conditions on signal assignments. This seems to imply
that the simulator would need to use delta cycle semantics
to determine the proper order of executing code. So where
the simulator can determine a proper ordering, it is
permitted to remove delta cycles so long as it preserves
changes with respect to time steps (time units not
delta cycles).
This works as long as nothing depends on delta cycles.
For RTL code, there is a delta cycle relationship between
clocks and data. For testbenches, some testbench handshaking
depends on delta cycles.
Clocks, Data, and delta cycles
To remove clock and data delta cycle dependencies,
we can identify clocks and derived clocks (as proposed
in a previous thread) and allow them to settle before other
delta cycles begin. This would also remove the need for
the "zero delay buffer" issue in PERF07.
Testbench Delta Cycle Handshaking
For my testbench approach, it does not look like it breaks
if delta cycles are removed from signal assignments. It does
depend on "wait for 0 ns ;" stopping for a delta cycle.
So as long as this is maintained, life is good.
If you are interested, further details of what I do for
delta cycle handshaking is at the end of the following paper:
http://www.synthworks.com/papers/VHDL_Subblock_Verification_DesignCon_2003_P.pdf
Time step delays need to be preserved:
Y <= '1' after 2 ns ;
In addition, perhaps we want to preserve delta cycle delays for:
Y <= '1' after 0 ns ;
This gives a way to force a cycle if needed.
Perhaps this would need to be an optimization that a
user can turn on with a command line switch and will
work provided a they have setup clocks with the
prescribed methodology.
Cheers,
Jim
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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