Subject: Re: [vhdl-200x-perf] Performance proposals
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Fri May 09 2003 - 16:48:18 PDT
> From: "john ries" <johnr@model.com>
>
> Hi All,
>
> I have posted an initial list of language changes to help performance.
> They are all just rough entries trying to capture the ideas that
> had been presented at the initial kick-off and working group
> meetings in February.
>
> What I need now is a discussion about the proposal and help
> to generate analysis of this proposal.
>
> Also any addition proposals would be warmly welcomed.
>
> Regards,
> John
> --
> -- mailto: johnr@model.com phone: (503)685-0864
> -- http://www.model.com fax: (503)685-0921
Some feedback:
PERF-01:
Is that a request for Verilog's blocking assign?
PERF-02:
I think you are just moving the evaluation code around
in your example it's hard to tell where you would get
a speed up - an optimizing compiler should give much
the same result either way. Having said that it looks
like a reasonable extension since it reduces complexity
from a user's perspective.
PERF-04:
Post elaboration optimization should handle that anyway,
do you really need a new class of signal?
PERF-06:
While it's good to remove unnecessary stuff, I'm not sure
how that improves performance much.
PERF-07:
Is there an actual proposal?
Personnally I think waiting for a design to be stable is
a bad idea - all you really know in a synchronous system
is that it should be stable by the next clock edge.
If you do PERF-01 then you can subdivide a delta by adding
implicit signals which indicate that a signal is about to
be updated or that it has been updated and all dependent
processes have executed e.g.:
clock'changing - sample data/assert last cycle done
clock - change clock value
clock'changed - assign sampled data etc.
I.e. all the processes sensitive to a 'changing signal are
processed before those sensitive to a regular signal, and
those sensitive to 'changed are done last.
PERF-08:
How does that enhance performance?
Regards,
Kev.
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