Subject: Re: [vhdl-200x-perf] Re: Performance issues
From: Paul J. Menchini (mench@mench.com)
Date: Wed Apr 30 2003 - 06:38:04 PDT
Steve,
> Would you get a race condition if you had unit delay? So this is kind
> of what I was talking about before you'd have to be a real expert to
> know to use a shared variable and then if you wanted to switch between
> accuracy and speed you would have to change your code (or make it much
> more complicated). It would be great if there was a simple switch or
> change of library that told the simulator to swap in all the tricky
> fast stuff and then go back to the slower more accurate models when
> you get near the end of your design cycle. Some way where all the
> expert trade offs for speed vs accuracy are done in the standard and
> the end user just has to specify the "fast" or "accurate" system.
No, you would not have a race condition if you introduced unit delay.
VHDL has these, but their called "delta delays." If you were to make
shared variables update only with unit delay, you'd then turn them into
VHDL signals.
As to the switch, there's nothing preventing vendors from doing this.
It would be an interesting question to ask them if they have, and if
not, why not.
Paul
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