Modeling and Productivity Language Enhancement ProposalsLast updated: 30-May-2003In the event this webpage is out of date, see also: directory listing of proposals The proposal template is here. This table is a work in progress. Items marked with "CCC" will be filled in later. |
| Index | Issue | Status |
|---|---|---|
| General Proposals | ||
| MP_CCC | Bidirectional Connections (Switch, Jumper, Resistor) | Listed |
| MP_CCC | Regularized and minimized bracketing (end) | Listed |
| MP_CCC | Allow concurrent assignments (conditional and selected) in sequential code | Listed |
| MP_CCC | Create a one dimensional array aggregate. Permit it to be used on LHS of assignment | Listed |
| MP_CCC | Permit expressions to be mapped to signal ports of entities and subprograms. | Listed |
| MP_CCC | Allow attribute declarations in code regions (not just declaration regions) | Listed |
| MP_CCC | More locally static expressions. Things like concatenation, indexing, and slicing of static objects/values | Listed |
| MP_CCC | Make transport the default delay model | Listed |
| Entity | ||
| MP_E1 | Allow ";" to terminate as well as separate interface lists | Listed |
| MP_E2 | Eliminate passive statement restriction on entities | Listed |
| Package | ||
| MP_CCC | Allow subprogram bodies in package declarations | Listed |
| Types, Operators, and Overloading | ||
| MP_CCC | Give bit_vector an unsigned interpretation. | Listed |
| MP_CCC | Create rising_edge and falling_edge for type bit. | Listed |
| MP_CCC | Integrate 1164, 1076.2, 1076.3 into 1076 | Listed |
| MP_CCC | Create comparision operators that return std_ulogic. ?EQ, NE, GT, LT, GE, LE? | Listed |
| MP_CCC | Boolean equivalence (short-hand for converting sl to boolean, if sl then) | Listed |
| MP_CCC | Ability to apply register kind semantics to std_logic. Retain last resolved value when all drivers are off. | Listed |
| MP_CCC | Remove white space requirement in physical literals. | Listed |
| MP_CCC | Short alias name for std_logic_vector. | Listed |
| MP_CCC | Value folding of std_ulogic (2 state/4 state). | Listed |
| MP_CCC | Max function | Listed |
| Generate | ||
| MP_CCC | Add else/elsif clause in if-generate. | Listed |
| MP_CCC | Case generate. | Listed |
| Components and Instantiations | ||
| MP_CCC | Implicit generic/port map in component instance | Listed |
| Process | ||
| MP_CCC | Permit keyword "all", or alternately symbol "*", in sensitivity list to imply all signals read in the process are in the sensitivity list | Listed |
| Case Statement | ||
| MP_CCC | Case statement expressions (index & choices) | Listed |
| MP_CCC | Don't cares in case statement targets and comparison operators | Listed |
| MP_CCC | Non-locally static expressions in case expressions. | Listed |
| If Statement | ||
| MP_CCC |
Add Endif (like elsif) See also general stuff about regularizing syntax and end |
Listed |
| MP_CCC |
Orif, orels, etc for mutual exclusive branches in FSM See one_hot |
Listed |
| Loop | ||
| MP_CCC | Longest static prefix issue with loops | Listed |
This table is a work in progress. Items marked with "CCC" will be filled in later.