Things such as implemented ranges for integer ports, or sizes for
unconstrained array ports, would be valuable to communicate up the
chain, in a static manner. I usually test these things with
assertions, but it would be nice to let the instantiator know so that
appropriately sized objects could be declared. I have no idea how big a
pain this would be to implement in the language, but I can imagine the
effect on the elaboration phase would not be trivial.
Another use of these could be in defining constraints on ports
themselves, based on the architecture.
Additional ability to declare an object's size based on an entity's or
component's port size would be helpful in the same vein, but probably
not necessary if the generic can be passed upward.
This may already be obvious, but the value should be able to be defined
in the architecture (somewhat like a deferred constant in a package
body) as well as the entity, such that it can be different for multiple
implementations of the same entity.
How would the generic's value be accessed in the instantiating
architecture? Would it be similar to defining a deferred constant in
the declarative region, then binding the constant to the generic in
the statement region via the generic map on the instantiated
component/entity? I assume out mode generic values could be defined
based on out mode generics from instantiated modules as well?
architecture instantiator of example is
constant limit : natural;
signal conduit: std_logic_vector(limit - 1 downto 0);
begin
e1: entity work.sub_module(rtl)
generic map (implemented_limit => limit)
port map (input, conduit);
...
end architecture;
Andy Jones
Lockheed Martin
Dallas TX
Tim Davis wrote:
Colleagues:
I accepted the task of putting a proposal together for out mode
generics for the VHDL-200x-MP (modeling and productivity) functional
team. To that end I'm soliciting input from users who think that out
mode generics would be a valuable enhancement to a future VHDL
standard. This request has two purposes: 1) to gauge any broad based
interest in
out-mode generics (hence this post to VHDL-200x), and 2) to locate a
couple of people to help me with the proposal.
Please email descriptions of how you would use out-mode generics to the
vhdl-200x-mp reflector. If you
know
of people in your organization who are interested in this topic please
have them contact me. They don't need to participate in the standards
development process to provide user input!
Thanks.
--
Aspen Logic, Inc.
By: Tim Davis, President
Received on Thu Apr 29 08:41:48 2004