Subject: Re: [vhdl-200x-mp] Analog/Digital conversion
From: Paul J. Menchini (mench@mench.com)
Date: Tue May 06 2003 - 11:06:08 PDT
Kevin,
>> Signal resolution occurs at each level in the hierarchy where a
>> signal in the net is of a resolved type. Driving values are
>> propagated upwards to the root signal. The driving value of the root
>> signal becomes its effective value, and that effective value is then
>> propagated down to the leaves.
> That's what I thought, it causes problems with AMS and bidirectional
> flow when it's done like that. For hardware modelling you really want
> to do resolution flat i.e. you consider all drivers at once and ignore
> the design hierarchy. In which case you have to do type conversion
> differently: each driver is individually converted to the domain/type
> of highest accuracy resolution is performed there and then the result
> converted back to give effective values, and to do that you need to
> mark the types as being "flat resolution" only and you need a type
> hierarchy to indicate relative accuracy (it's easy in Verilog-AMS
> because there are only two types).
My comments applied to VHDL signals only. Analog modeling in VHDL AMS
uses terminals. Terminals have their values computed differently than
signals.
Paul
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