IEEE P1164 Working Group - Change Proposal

ID:	  CP-004

Proposer: EIAJ

Status:	  Proposed (1-Jun-2001)
	  Analyzed (07-Dec-2002)
	  Resolved (17-Feb-2003)

Summary:  Add capacitive drive strength

Detail:

(From slides presented at VIUF-1999)

Proposed by the EIAJ to enable simulation of dynamic and switch level
effects (http://vhdl.org/libutil/mvl12.vhd)

One additional strength i.e. 3 additional meta values 'C', 'D' and 'P'

    type std_ulogic_d is
      ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', 'C', 'D', 'P' );

Upward compatibility possible using the VHDL subtype concept similarly
as X01, X01Z, UX01 and UX01Z subtype

    subtype std_ulogic is std_ulogic_d range 'U' to '-';


Is the additional strength sufficient?

  - Two additional strengths requires only 15 (< 16) values
  - Verilog has 10 strength
  - Infineon analog designers think of about 1000 strengths as
  - suitable

SDF / VITAL doesn t support that number of strengths!


Need more study (justification, how many strengths, possibility of new
package?)


Analysis:

	By Peter Ashenden <peter@ashenden.com.au>, 07-Dec-2002

	This is a major change to the standard package.  Given the
	short timeframe for the current revision, further analysis of
	this proposal should be deferred to the next revision of the
	standard.


Resolution:

  Analysis accepted

  Member votes: Accept 13 (100%)   Reject 0 (0%)   Abstain 0 (0%)
  All votes:    Accept 14 (100%)   Reject 0 (0%)   Abstain 1 (7%)

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