RE: [vhdl-200x-ft] Case? statements and selected assignments

No objections.  It sounds like the right thing to do.

-Steve Bailey 

> -----Original Message-----
> From: owner-vhdl-200x-ft@eda.org 
> [mailto:owner-vhdl-200x-ft@eda.org] On Behalf Of Peter Ashenden
> Sent: Tuesday, April 05, 2005 2:49 AM
> To: vhdl-200x-ft@eda.org
> Subject: [vhdl-200x-ft] Case? statements and selected assignments
> 
> Folks,
> 
> In FT24, we propose a case? statement that allows for 
> don't-care matching using the ?= operator.  In preparing an 
> LCS for this, I found it appropriate to describe case? as a 
> variant of the existing case statement, sicne most of the 
> rules are the same.  I just added a ? delimiter as optional 
> syntax after the case keyword.
> 
> That made me think that we should then formulate don't-care 
> matching variants of selected signal and variable 
> assignments.  Doing so would complete the correspondences.  
> It would simply require saying that if a ?
> appears in the selected form, it also appears in the 
> equivalent form.  For example,
> 
>   with E select?
>     S <= bla1 when "00--",
>          bla2 when "01--",
>          bla3 when "1---";
> 
> would be equivalent to
> 
>   case? E is
>     "00--" => S <= bla1;
>     "01--" => S <= bla2;
>     "1---" => S <= bla3;
>   end case?;
> 
> and similarly for a selected variable assignment.
> 
> Any objection to persuing this?
> 
> Cheers,
> 
> PA
> 
> --
> Dr. Peter J. Ashenden                        peter@ashenden.com.au
> Ashenden Designs Pty. Ltd.                   www.ashenden.com.au
> PO Box 640                                   Ph:  +61 8 8339 7532
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> Australia                                    Mobile: +61 414 70 9106
> 
>