Re: [vhdl-200x-ft] numeric_bit package

From: Jim Lewis <jim_at_.....>
Date: Tue Mar 01 2005 - 10:00:12 PST
David,
> In numeric_bit (SIGNED and UNSIGNED types using BIT_VECTOR logic) we
> have the following functions:
> 
>   -- Id: S.9
>   function "sll" (ARG : UNSIGNED; COUNT: INTEGER) return UNSIGNED;
>   -- Id: S.10
>   function "sll" (ARG : SIGNED; COUNT: INTEGER) return SIGNED;
>   -- Id: S.11
>   function "srl" (ARG : UNSIGNED; COUNT: INTEGER) return UNSIGNED;
>   -- Id: S.12
>   function "srl" (ARG : SIGNED; COUNT: INTEGER) return SIGNED;
>   -- Id: S.13
>   function "rol" (ARG : UNSIGNED; COUNT: INTEGER) return UNSIGNED;
>   -- Id: S.14
>   function "rol" (ARG : SIGNED; COUNT: INTEGER) return SIGNED;
>   -- Id: S.15
>   function "ror" (ARG : UNSIGNED; COUNT: INTEGER) return UNSIGNED;
>   -- Id: S.16
>   function "ror" (ARG : SIGNED; COUNT: INTEGER) return SIGNED;
> 
> These functions are in the original 1076.3 specification.  According to
> our conversation in the telecon last night, they are implicit.  Should
> I comment them out?
The types signed and unsigned (although based on bit in numeric_bit)
are distinct types and require these functions to be implemented, otherwise,
they are not defined.

The only ones that are implicit are the ones that are of the form:
    function "sll" (ARG : bit_vector; COUNT: INTEGER) return bit_vector;

Further, my memory of the meeting is that we want to overload these in
numeric_bit_unsigned to make the implementation the same as for type
unsigned.   Per FT1, it is ok to create an explicit overload that replaces
an implicit overload.


> Also, we have
>   -- Id: E.1
>   function RISING_EDGE (signal S: BIT) return BOOLEAN;
>   -- Id: E.2
>   function FALLING_EDGE (signal S: BIT) return BOOLEAN;
> 
> Since we have moved these functions into std.standard there will be
> a conflict if these are visible.  I will comment them out.

Agree.


If anyone has a conflicting memory of the meeting please speak up.

Cheers,
Jim
-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
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Received on Tue Mar 1 10:00:15 2005

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