Hi David & Collin, Thanks for your replay. Collin, it's true that you can convince Cadence BuildGates to not write out netlists with negative indexes with set_global hdl_verilog_out_no_negative_index true. But it's the only synthesis tools which have a such command. Synopsys or Cadence RTL Compiler doesn't have a similar one. Don't forget that converting negative indexes to positive indexes complicates a lot the formal verification between the original vhdl and the netlist. David, concerning Synopsys I can guaranty you that even with (hdlin_enable_presto_for_vhdl = true) you can't compile "in1reg3 = in2reg3 + 3.1415". When I try to compile with synopsys (version 2004.12 or earlier) I get this error message : Generic error: REAL is not supported in synthesis. ELAB-2. I will put for you in attachment with this mail 2 testcases (one which doesn't use any real ("test_constant_reals_std2.m.vhdl") and one which use them("test_constant_reals_std.m.vhdl")). The synthesis result of the 2 testcases must be the same but the only the one that doesn't use real ("test_constant_reals_std2.m.vhdl") can be synthesised with Synopsys. Could you take a look and see from your side? Kind Regards, Yannick --------------------------------------------------------------------------------------------------------- Yannick Grugni Design Competence Center Leuven VLSI Engineer Interleuvenlaan 74-82 Tel: +(32)16.390.742 3001 Leuven yannick.grugni@philips.com Belgium ----------------------------------------------------------------------------------------------------------
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