Re: [vhdl-200x-ft] Questions/Remarks concerning fixed_pkg

yannick.grugni@philips.com writes:

> I have some questions/remarks concerning your fixed_pkg.
[...]
> 5.a) The first problem concerns negative index. A negative index in vhdl 
> will stay a negative index in verilog after synthesis. The problem is that 
> some backend tools doesn't like netlist containing negative index.

FWIW, you can convince Cadence BuildGates to not write out netlists
with negative indexes with

  set_global hdl_verilog_out_no_negative_index true

There should be some page that lists such problems and workarounds,
but it's probably not within the scope of eda.org or the IEEE.  Maybe
something like the VHDL FAQ.

Cheers,
  Colin