Hi,
Please find below some examples of aggregates that are, I think, not legal
in vhdl 87 and 93.
Do you have intention to allow those kind of codes in the next vhdl
standard.? I think, It would be nice .
CASE 1)
procedure (b,c : out signed)
begin
b :=(OTHERS => '0'); -- not legal because b is unconstrained
c :=('1',OTHERS => '0'); -- not legal because b is unconstrained
end;
--------------------------------------
CASE 2)
generic n : integer := 3;
...
signal a : unsigned(n downto 0)
constant b : unsigned(n downto 0) := ('1',OTHERS => '0'); -- not legal
because n is not locally static
...
a<= ('1',OTHERS => '0'); -- not legal because n is not locally static
--------------------------------------
CASE 3)
signal pos : integer := 3;
signal a : unsigned(7 downto 0)
...
a<= (pos => '1',OTHERS => '0');
--------------------------------------
Kind Regards,
Yannick
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Yannick Grugni Design Competence Center
Leuven
VLSI Engineer Interleuvenlaan 74-82
Tel: +(32)16.390.742 3001 Leuven
yannick.grugni@philips.com Belgium
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Received on Wed Feb 2 07:05:04 2005
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